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9th November 2019, 06:59 #1
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How to generate sine wave using Verilog?
I have to generate a two different sine wave(1st sine wave normal sine wave which is generate from 0 degree and 2nd one phase shifted sine wave ) using Verilog, and on google, I found something related to it but somehow I didn't understand. So, could anyone explain to me the logic behind this code?
Code:module sine_cos(clk, reset, en, sine, cos); input clk, reset, en; output [7:0] sine,cos; reg [7:0] sine_r, cos_r; assign sine = sine_r + {cos_r[7], cos_r[7], cos_r[7], cos_r[7:3]}; assign cos = cos_r  {sine[7], sine[7], sine[7], sine[7:3]}; always@(posedge clk or negedge reset) begin if (!reset) begin sine_r <= 0; cos_r <= 120; end else begin if (en) begin sine_r <= sine; cos_r <= cos; end end end endmodule
but here what is the logic for ?
assign sine = sine_r + {cos_r[7], cos_r[7], cos_r[7], cos_r[7:3]};
assign cos = cos_r  {sine[7], sine[7], sine[7], sine[7:3]};

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9th November 2019, 08:26 #2
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Re: How to generate sine wave using Verilog?
Hi,
I expect there is some description where you found the code.
> please post the link to the internet page.
KlausPlease donīt contact me via PM, because there is no time to respond to them. No friend requests. Thank you.

9th November 2019, 12:25 #3
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Re: How to generate sine wave using Verilog?
The oscillator operation has been discussed in previous threads, e.g. https://www.edaboard.com/thread39599.html
The Verilog implementation is somehow clumsy, the function can be made much clearer by using signed data type.
   Updated   
Code Verilog  [expand] 1 2 3 4
output signed [7:0] sine,cos; reg signed [7:0] sine_r, cos_r; assign sine = sine_r + (cos_r >>> 3); assign cos = cos_r  (sine >>> 3);
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9th November 2019, 15:12 #4
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Re: How to generate sine wave using Verilog?
Consider that the derivative (slope) of sin is cos and the derivative of cos is sin. Thus you can increment one by a value proportional to the other and you get a selfoscillating output that's a very good (not perfect) sin wave.
The specific code you're questioning is just a power of 2 divide. FvM posted a better way to do this. The more you divide the longer the period is.
The biggest problem is rounding errors. You need to get lucky and find a set of parameters that returns exactly to where it started or you need to reset every cycle introducing a small amount of distortion. If you don't the amplitude will 'walk away' towards zero or infinity.
Bottom line this is a very 'cheap' way to generate a sin wave in an FPGA. For high precision work you're best off using the IP blocks that all FPGA manufacturers provide.Last edited by asdf44; 9th November 2019 at 15:21.
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10th November 2019, 09:28 #5
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10th November 2019, 10:40 #6
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Re: How to generate sine wave using Verilog?
>>> is arithmetic shift, >>> 3 means multiply with 0.125.
For a deeper insight how it works please review the linked old thread.
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15th November 2019, 19:47 #7
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How to generate Square wave from Sine wave in verilog ?
Here by using a just normal procedure for generating sine wave , through verilog code. " i have to generate a two different sine wave , 1st normal sine wave (which is start from 0 degree ) and 2nd wave which is start from phase shift(+ 90 degree) sine wave.and that i already done in vivado simulation but Now i want to again generate a square wave from this sine wave, (sine wave > counter ) so please suggest me the logic for verilog !

16th November 2019, 05:46 #8
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Re: How to generate Square wave from Sine wave in verilog ?
same frequency?
sketch the sin wave, then sketch the square wave on top of it. where along the sin wave if the square wave high? when low?
now write the appropriate logic statements
different frequency?
how do you get from the sinwave frequency to the square wave frequency?

16th November 2019, 11:38 #9
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Re: How to generate sine wave using Verilog?
but now i want to again generate a square wave from this sine wave

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16th November 2019, 15:03 #10
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Re: How to generate sine wave using Verilog?
as FvM says, use the sign bit
you specified sine and cos as signed values, so the square waves will be specified by sign + or 
use a statement that checks the sign bit, as FvM suggested
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