Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] [moved] What is Cadence genus synthesis, report power?

Status
Not open for further replies.
D

daskk62

Guest
I have written a verilog code of a counter, and I have done the synthesis of that counter code using Cadence Genus tool. Now I want to calculate the power. For that I have used the command report power and got the leakage power, dynamic power, mainly total power consumed what I actually want. Now my question is whether this power is related to any clock frequency, if so how?
 

I have written a verilog code of a counter, and I have done the synthesis of that counter code using Cadence Genus tool. Now I want to calculate the power. For that I have used the command report power and got the leakage power, dynamic power, mainly total power consumed what I actually want. Now my question is whether this power is related to any clock frequency, if so how?

you must have set the clock somewhere in your synthesis script or through an external sdc file. check what value you have used. dynamic power is a function of the clock frequency, no doubt about it.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top