sonika111
Member level 2
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 signal count :std_logic_vector(1 downto 0):= "00"; -- Enumerated type declaration and state signal declaration type States is (S0,S0a, S1, S2, S3,S4); signal nState, cState: states; begin state_reg: process(clk, Reset) begin if (Reset = '1') then cState <= S0; elsif (clk'event and clk = '1') then cState <= nState; end if; end process; comb_logic: process(cState) -- variable count : integer range 0 to 7:= 0; begin case cState is when S0 => counter <="00"; Strobe <= '0'; if (count < "11") then count<= count + "01"; nState <= S0; else nstate <= S1; count <="00"; end if; when S1 => counter <= "01"; Strobe <= '0'; nState <= S2;
Hi there
my problem here is I want to introduce a delay of about 3 cycles for state to go from S0 to S1; I have introduced count to do that. But even if I use it as a signal or variable; I am unable to increment count and if statement doesn't become true and I am unable to go to next state.
If you could please help me debug what I am doing wrong; it would be great
Thanks very much
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