Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

vhdl problem debug help please

Status
Not open for further replies.

sonika111

Member level 2
Joined
Jan 11, 2011
Messages
50
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,716

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
signal count :std_logic_vector(1 downto 0):= "00";
     -- Enumerated type declaration and state signal declaration
    type States is (S0,S0a, S1, S2, S3,S4);
   signal nState, cState: states;
 
begin  
    
    state_reg: process(clk, Reset)
    begin
        if (Reset = '1') then 
            cState <= S0;
 
        elsif (clk'event and clk = '1') then 
            cState <= nState;
 
        end if;
    end process;
 
    comb_logic: process(cState)  
   
  -- variable count : integer range 0 to 7:= 0;  
    begin
 
      case cState is 
            
    when S0 =>      counter <="00";
                         Strobe <= '0';
                if (count < "11") then
                    count<= count + "01";
                        nState <= S0;
                else
                 nstate <= S1;
                                 count <="00";
                end if;
        
    when S1 =>  counter  <= "01";   
                     Strobe <= '0'; 
              nState <= S2;



Hi there

my problem here is I want to introduce a delay of about 3 cycles for state to go from S0 to S1; I have introduced count to do that. But even if I use it as a signal or variable; I am unable to increment count and if statement doesn't become true and I am unable to go to next state.

If you could please help me debug what I am doing wrong; it would be great

Thanks very much
 
Last edited by a moderator:

You need to have "count<=count+"01" in a clocked process, not a combinational process.

And have you included ieee.numeric_std? Have you observed the value of "count"? Is it incrementing? Probably not.
 

Put the counter in a clocked process - you cannot do a counter in a combinatorial process. It is not updating because you forgot to add count to the sensitivity list, but if you do, you'll get an infinite loop because counters cannot be incremeneted combinatorially.
 

You need to have "count<=count+"01" in a clocked process, not a combinational process.

And have you included ieee.numeric_std? Have you observed the value of "count"? Is it incrementing? Probably not.

Thanksvery much for your reply

Its value remains 1. I don't know why?

What library should I be using ?

How do I change the above code so that I can introduce a delay of a=say 3 clock pulses between S0 to S1?

- - - Updated - - -

I tried putting


Code VHDL - [expand]
1
2
3
4
5
6
7
8
if (Reset = '1') then
cState <= S0;
 
elsif (clk'event and clk = '1') then
cState <= nState;
Count <= Count + "01";
end if;
end process;



and changed my combinational process a bit to accomodate this change but it did not help.....

If I use a variable count with in the comb_process it didnot help either; I don't know why?
 
Last edited by a moderator:
  • Like
Reactions: ads-ee

    ads-ee

    Points: 2
    Helpful Answer Positive Rating
I, for one, never use separate clocked/combinational process for state machines. I know all the literature says this is the way to do it, but I find it's always a problem (just like what you're seeing here).
So, as was previously stated, put the counter in a clocked process, and use ieee.numeric_std
 

Untested but your code should be something like this for a counter using your 2 process FSM style.

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
if (Reset = '1') then
  Count <= (others => '0');
elsif rising_edge(clk) then -- this is the recommended way to detect a rising edge it only triggers if transition is 0 => 1.
  if cState = S0 and Count < "11" then -- it has to be done when your FSM is in the S0 state
    Count <= Count + "01";
  else
    Count <= (others => '0');
  end if;
end if;

 

Thanks very much, I will give it a go if not 1 will try writing in 1 process FSM style
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top