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SMD Sync Buck converters with parallel FETs and no heatsinks

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treez

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Why do you rarely get low voltage all-SMD sync buck schematics with say three SMD power FETs in parallel?
Surely, paralleling SMD FETs here is the way forward as it allows the solution to avoid using a FET heatsink, which would significantly up the cost.
 

some fets just don't like being hard paralleled, even with 10 ohm gate R's with a batch change you can get a lot of 100MHz gate and drain ringing and increase RFI and field failure ( I recently looked at this for a VERY large DC motor controller manufacturer - after a die shrink in the fets they bought ...! )
 
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Thanks, if not being paralleled, then what generally do you take as being the maximum power dissipatable in say a DPAK FET on a 2 layer FR4 PCB with no heatsink, and with it just having thermal copper surrounding it up to 1cm all round, and the bottom layer copper mirroring this area, with thermal vias interconnecting? (1 oz copper on PCB, 1.6mm thick PCB, No fan).
Consider the PCB in a metal enclosure, but not thermal padded to it, and the external ambient being 30 degC....Internal ambient 50degC.

some fets just don't like being hard paralleled, even with 10 ohm gate R's with a batch change you can get a lot of 100MHz gate and drain ringing and increase RFI and field failure
Thanks, so you mean one batch of FETs would not dipsplay the ringing, but another batch of the same FETs would show the ringing if hard paralleled....thats bad news.......coudl be very expensive in terms of field failures.

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The following article suggets that in sync bucks, paralleling fets is ok…maybe the parallel fet problem occurs in other types of converters and not in sync bucks?

https://www.ti.com/lit/wp/snva595a/snva595a.pdf

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The alternative to paralleling, is heatsinking, which is too expensive for us in this application...so the only other alternative is paralleled converters...which is many more components and needs the current sharing circuitry
 
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Speaking from experience of a recent paralleling fail the problem with paralleling small SMT parts is the watts density. They must be close for good performance so the result is minimal decrease in power density. 2 parts on 2cm^2 isn't going to be much better than 1 part on 2cm^2 of copper.


For a DPAK you're talking 1-4 watts or so depending on your ambient and thermal rise tolerance. Perhaps on the lower end based on what you said.


I don't know why you've ruled out heatsinks..cheap heatsinks cost less than a FET and will actually get rid of watts. Clip-on TO-220 sinks are similar price with minimal installation labor.
https://www.digikey.com/product-detail/en/assmann-wsw-components/V-1100-SMD-A-L/A10760-ND/3476156

If you're really tight for cost throw much more copper at it than 1cm and throw in as many vias as possible (vias in pad if possible). Other tricks (I've done these): place fets on bottom with many vias and extruded heatsink on top. Squishy thermal pad to chassis either on top of the parts or under them (lots of vias again).

A handful of silicon fets have top side cooling which could be coupled to chassis or a cheap extrusion. Most GAN parts are easier to cool (plus more efficient): Transphorm has SMT parts with source as the pad (sinks to the ground plane), EPC has same number of S and D pins so half of them will be sunk to a plane, Gan systems has good top side cooling.


Finally I'll suggest interleaving. This avoids additional losses associated with imperfect paralleling and lets you spread the parts out so you should actually increase dissipation. Many boost controllers already support interleaving right?
 

thanks, all your ideas are great...thing is, in this case, any manual-labour heatsinking in the production assembly is going to knock the cost too high....the customer already has a solution and wants this alternate way using sync bucks to be looked at in case its cheaper.
Its four separate 25w sync bucks, 24vin to 4vout.
Everything must be SMD, otherwise it'll be too pricey.

I have seen app notes that describe that thermal coper is only good to about 1 inch outside the part............so we are thinking of paralleling to reduce overall rdson...or just using a single DPAK, or one of these QFN type FETs.
Paralleling seems the most bona fide way to manage the heat....but if its going to be ringing like mad on the gate then we are well stuck.
I cant think why it would ring just because there are two paralleled fets instead of one single one?....if we do the layout tight. Its only 25w.
 

What about the SMT heatsink? It's just another SMT part that comes right off the line.

Ok here is the app note I was looking for. This has Tja for DPAK (page 33) versus copper area from 0-600mm^2:
https://www.infineon.com/dgdl/smdpack.pdf?fileId=db3a304330f6860601311905ea1d4599

The key is that if you add a second fet you have to spread it out, which isn't ideal from a layout perspective.

Note that at 57C/W with 600mm^2 you can only get a watt or 2. The heatsink linked above lists 23C/W. That's a lot more cooling bang for the buck than a second fet even if you have another 600mm^2 to give it.
 

Some brands tolerate paralleling much better than others - it is a trial and error thing ... at least 3.3 ohms on each gate though ...
 

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