Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Analog Layout - Sharing source/drain

Status
Not open for further replies.

big_fudge98

Member level 2
Joined
Mar 31, 2019
Messages
43
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
445
Hi all,

I have recently done layouts of some analog blocks such as op-amps, current source etc. Upon getting them reviewed by an experienced individual from the industry, I recieved the following comments:

1) Do not share source/drain terminals and instead use multipliers.
2) Do not share dummy transistor source/drain. Instead keep minimum spacing between dummies and design transistors. Short dummies to VSS/VDD (NMOS?PMOS).

Unfortunately, I could not ask him the reason for his comment. Does anyone know why?

Thanks.
 

1) not exactly true, useage of fingers has the advantage they need less area and the parasitics are smaller. disadvantage can occour when matching is the main viewpoint, with odd and small number transistors the mismatch is worse as I know if they are fingered.
2) I only agree with the short. It is not preferred to let any gates floating, if you short all terminals together to VDD(PMOS)/VSS(NMOS) it is guaranteed the device won't be open and won't consume current, very simple way to prevent it. With the source/drain sharing of dummies I don't have experience, I have never heard about it. I guess if you have to use not fingered devices for example for better matching, the dummies should be similar, that is why he said.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top