+ Post New Thread
Results 1 to 3 of 3
  1. #1
    Member level 2
    Points: 461, Level: 4

    Join Date
    Feb 2019
    Posts
    51
    Helped
    0 / 0
    Points
    461
    Level
    4

    How I can make use of the resources of only certain regions of the device in Vivado?

    Greetings ... tell you that a few days ago I translated a single verilog file to vhdl to add it to my vhdl project in Vivado 2017.3 which has the function of controlling the transmission and reception of data for a hotlink interface, apparently no problem in simulation , synthesis and implementation through a tcl scritp, but when testing it in the hardware I observe that the transmission speed dramatically reduces. I was suggested to analyze the design of the project implemented in the device and in this way verify that the design had changed with respect to a version that still used the verilog file, as shown in the attached image.

    Click image for larger version. 

Name:	implemented_design.PNG 
Views:	3 
Size:	253.2 KB 
ID:	156303

    The truth is that I am new to the area of implementation and would like to know how I can make use of the resources of only certain regions of the device?

    •   AltAdvertisement

        
       

  2. #2
    Super Moderator
    Points: 32,120, Level: 43
    ads-ee's Avatar
    Join Date
    Sep 2013
    Location
    USA
    Posts
    7,427
    Helped
    1742 / 1742
    Points
    32,120
    Level
    43

    Re: How I can make use of the resources of only certain regions of the device in Viva

    You can use pblocks. As a starter you can read over this document. Search for pblock to get some information on it, then you can look for it in some of the other documentation.

    You might want to try searching for pblock using the Xilinx Document Navigator.



    •   AltAdvertisement

        
       

  3. #3
    Advanced Member level 5
    Points: 38,244, Level: 47
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,922
    Helped
    2036 / 2036
    Points
    38,244
    Level
    47

    Re: How I can make use of the resources of only certain regions of the device in Viva

    What is your goal?
    It is normal that a implemented design changes between builds because placement relies on a random seed. If the source code, constraints or seed change, then the final result will be different to a previous build.
    Are you assuming that because the implementation has changed your design no longer works? If your design uses fully synchronous design and is properly constrained, if the design meets timing then it should work every time. If it is not working, I suggest there is a problem with the code or lack of timing specs. Using pblocks may help only by masking the problem in specs or source code.

    So, what exactly is the problem (pblocks are not usually the answer to anything).



--[[ ]]--