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[SOLVED] Protect FPGA Pin from negative voltage

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clros

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Hi to all,

In a my project I am using an Altera/Intel Cyclone IV FPGA.

For some reason, the IO pins can be drivered with a negative voltage (-3.3V) that I would is interpreted as logic level 0.

The problem is that the IO pins of FPGA not support negative voltage.

I see in some circuit, that it used the BAT54 diode for protect the IO pins.
I have simulated the circuit and the voltage, if I use the BAT54, is only -400mV.

It is a good solution?
 

Hi,

A BAT54 only won't work. You need some current limiting device. Usually a series connected resistor.

if I use the BAT54, is only -400mV. It is a good solution?
Simple answer: If the voltage level is within the specified input voltage range of the FPGA, the yes.

That's why there are datasheets.
And this is not meant as offence...this is the way I (heve to) do it all the time.

Klaus
 
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    clros

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Thanks for response.

Altera datasheet says thar minimum voltage on its IO pins is -0.5V.

ButI didn't understand how to insert the resistor ... in series with diode (towards ground) or in series with the FPGA pin?

Annotazione 2019-11-01 121508.png
Annotazione 2019-11-01 121409.png

And...the correct value of resistor?
 

BAT54 directly between the FPGA pin and GND. The resistor is only necessary if the current through the BAT54 will be too high (set the limit somewhere in the range 1-10mA) without it.
The resistor should then be placed in series with the conductor going to "From my circuit".
When you got -400mV there were obviously something that limited the current, so it was probably OK without an additional series resistor.
 
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    clros

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The resistor is only necessary if the current through the BAT54 will be too high (set the limit somewhere in the range 1-10mA) without it.

I simulated without FPGA, but with a load of 1MOhm // 6pF (that should be the impedeance of FPGA IO pins).

The current thath I see in simulation is maximum of -14mA. If I understand well, the BAT54 datasheet (https://www.vishay.com/docs/85508/bat54.pdf) report maximum current (Forward continuous current) of 200mA.
It is the correct parameter (Forward continuous current) that should I check?
 

You must also look at the Vf/If diagram. To keep Vf below 0.5V, the current can only be a few tens of mA.
I suggest that you make sure that the current in the diode never exceeds 1-10 mA (you select the exact value).
 
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    clros

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BAT54 is fine if the signal speed isn't too high. You didn't yet mention the input frequency or minimal pulse width.
 

Hi,

You said that the applied voltage may be down to -3.3V.

This is what is given.

If you don't have additional information you need to expect a very stable = low ohmic voltage source (worst case scenario).
Now if you want the BAT54 voltage to be less than 0.4V....
--> then you need to install a current limiting resistor between the -3,3V source and the "-0.4 V" BAT signal.
The voltage across the resistor is -3.3V - (-0.4V) = -2.9V.
Ignore the sign.... fir further calculation use 2.9V.

Then maybe you want to keep current below (let's say) 15mA..... just use Ohm's law to calculate the resistor value:
= 193 Ohms. With a 200 Ohms resistor you are safe.

Klaus
 
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A resistor alone is often enough to protect against voltage (by limiting current to below the specified limit, often 10mA).
 

BAT54 is fine if the signal speed isn't too high. You didn't yet mention the input frequency or minimal pulse width.

I should use a maximum frequency of 3 MHz.
How I understand if the BAT is adequate?
 
Last edited:

Hi,

We already did discuss about voltage and current.

What else: the next is frequency...
This is determined by source resistance and load capacitance

Klaus
 

--> then you need to install a current limiting resistor between the -3,3V source and the "-0.4 V" BAT signal.

Annotazione .png

This is the correct connection?

In this case, the logic level 1 (in my case +3.3V) will have a lowering and will not come with its value (+3.3v) to the FPGA.
I hope this won't cause problems. But I guess this is inevitable. Quite right?

- - - Updated - - -

Hi,

We already did discuss about voltage and current.

What else: the next is frequency...
This is determined by source resistance and load capacitance

Klaus

For driving my FPGA I am using the OpAmp TLV274 (https://www.ti.com/lit/ds/symlink/tlv274.pdf). I do not know how to determine the source resistance.
For the load capacitance, from Altera datasheet, It should be 6pF.
 

You do not want to be in a "diode vs diode foot race" thinking
you're going to prevent latchup. Differences between chip and
diode junction temp, or just a bit too much overshoot
(undershoot) and the external diode may not take all of the
trigger current.

How about a resistor divider pinned to I/O supply, such that
low comes in around I/O ground, and high (which is ??? at
the source) exceeds VIH(min)?

Another option if signals are slow enough, is to use a diode
network to stand off negative, but push positive, to the pin.
Again this needs to declare the two input levels. You can
see schemes like this used in "5V tolerant" low voltage
CMOS input buffers.

You could also consider purpose-made level shifter ICs,
maybe a (say) ECL to LVCMOS would have the voltage
domain tolerances you need, as well as well defined
datasheet / behaviors.
 

Hi,

In this case, the logic level 1 (in my case +3.3V) will have a lowering
Why? Please explain.

I hope this won't cause problems.
A good engineer does not rely on "hope". ;-) He uses the datasheet. --> Check V_IH_min.

Klaus
 

Hi,

Why? Please explain.

I think that there is a voltage drop on my resistance. Am I wrong?

A good engineer does not rely on "hope". ;-) He uses the datasheet. --> Check V_IH_min.

Unfortunately I'm not an electronic engineer, I'm a programmer who delights in hardware!

For this reason, my questions are probably stupid!
 

Hi,

I think that there is a voltage drop on my resistance. Am I wrong?
A voltage drop only happens when there is current.
So what current do you expect?
Let's use your input resistance of 1MOhms ... then it will be 3.3uA worst case.
On a 200 Ohms resistor this means a voltage drop of 660uV..this is less than 1mV.
So with 3.3V .... the input voltage is 3.29934V

All the calculations above are just according Ohm's law. You need to learn this basic formula. This really is urgent.

Unfortunately I'm not an electronic engineer, I'm a programmer who delights in hardware!

For this reason, my questions are probably stupid!
Not stupid.

The question is: How do you want to go on in future?
Ohm's law is basic and not difficult,
Reading datasheets is not difficult either, as a long as you do know what to look for.
Input voltages: V_IH, V_ IL
Output voltages
Input currents.

But avoid one often made mistake:
If you want to look for typical operation conditions then don't look in the "absolute maximum values" section.

I'm sure you can solve similar problems on on your own.

Klaus
 

Hi,


A voltage drop only happens when there is current.
So what current do you expect?
Let's use your input resistance of 1MOhms ... then it will be 3.3uA worst case.
On a 200 Ohms resistor this means a voltage drop of 660uV..this is less than 1mV.
So with 3.3V .... the input voltage is 3.29934V

Ok.
For this reason, can I to use a Greater resistor (470 ohm)? The drop voltage should be acceptable, the current through diode BAT is lower and the voltage is less than -0.4V and I are secure with the FPGA protection...
 

Hi,

For sure you may use higher ohmic resistor.

The drawback is: the higher the resistor value, the lower the cutoff frequency.
It is a first order LPF created by the resistor and the capacitance (FPGA_input_capacitance, BAT54_capacitance, wiring capacitance, mainly).
Mind: a square wave is a combination of the fundamental frequency sinewave plus it's overtones. If you cut off the overtones it is no square wave anymore. A little deformation my not hurt .... but in detail it depends on your application.
--> choose f_c to be (much) higher than your square wave frequency.

Klaus
 
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