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Timing constraints using a PLL.

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Pastel

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Hello!


There is something a little bit unclear to me.
When I started programming a few months ago, I made a generator for arbitrary
signals. In order to check how it works, I have loaded a sine wave and the
generator just addresses the array and sets the address to a DAC.
At one point, it stopped working, I had a really weird output. After some
search on the web, I found out that the timing might not be optimal, so I
learned how to set time constraints, which fixed the problem. Basically,
the distance between data vs clock of the DAC I use are important, and
this makes constraints between system clock and DAC clock.


Now I have tried something else on a copy of the original project. I didn't set any time
constraints, but the PLL I use allows me to accurately set the phase between
one signal and the master clock. This method also fixes the problem, and depending
on the phase I set, the output might be nice or completely screwed up.

NB: In my application, I generate sys_clk and dac_clk from the physical input clk.
Both are generated by the same PLL, I can be sure of their relationship (phase),
and I verified it on the scope.


As PLLs allow me to build any kind of signal with any phase, I can tune the distance
between the edges of the DAC, so this method also seems valid to me. Is this a good
method to set time constraints? What would be the drawbacks of this method?


Thanks for any hint.


Pastel
 

This is NOT a good method. What may work for one build may not work for the next. Change one little thing and the routing can change completely and since you’ve got no constraints there is nothing to guarantee you’ll have the same phase relationship.
 

Hello Barry!

since you’ve got no constraints there is nothing to guarantee you’ll have the same phase relationship.

Do you mean that the phase as defined in the configuration panels of a PLL is not reliable?
I have verified that the phase set by the PLL definition is coherent with what I observe on the
scope. Do you have any example of a PLL with a phase which doesn't correspond to its settings?

NB: I'm sure that there is a good reason for the time constraints config, and therefore I'm back to the
version with the timing constraints, but I would like to understand where it could go wrong.

Thanks!

Pastel
 

The phase of the PLL is relative, either to its input clock or a secondary output clock. Once you route those signals, with no constraints, there’s no guarantee that phase stays the same. It’s like saying two trains leave the station at the same time, but one takes the scenic route. They’ll both arrive at the destination, but not at the same time.
 

There is something a little bit unclear to me.
When I started programming a few months ago, I made a generator for arbitrary
Based on your own description of what you are currently doing, you've been writing software prior to FPGAs. You are now thinking of HDLs as programming, you are writing hardware descriptions in a language that sort of appears to be a programming language.

As the HDL description is applied to hardware you need to meet setup and hold time of registers, deal with clock domains and crossing them, deal with the phase relationships between signals, and timing in and out of the part to other devices outside the FPGA (this is only the basics of what you may need to be aware of). Every line of code you write in an HDL must represent some equivalent digital circuit, that is made up of RAMs, ROMs, flip-flops, multiplexers, decoders, gates, etc.

The timing constraints are used to ensure from place and route run to run that the requirements of both the internal FPGA logic and the external devices is met so the design functions across PVT (process, voltage, & temperature). Without those constraints the tools do whatever they want, which is usually not what you want.
 

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