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  1. 29th October 2019, 08:06 #1
    anas171
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    CMOS varactor in cadence

    Hi all,
    I want to design an NMOS varactor in Cadence. where the source and drain of NMOS are shorted together like the attached figure. And the gate is controlled by another voltage. I have all the required parameters of this S/D gate NMOS varactor.

    I want to know how do I plot the Cv vs Vgb for this MOS varactor with different (W/L) values like the attached figure. It will be very helpful if anyone can point out the steps serially how to simulate this MOS varactor in UMC 130nm process with Cadence.
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  2. 29th October 2019, 09:05 #2
    pancho_hideboo
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    Re: CMOS varactor in cadence

    Quote Originally Posted by anas171 View Post
    I want to design an NMOS varactor in Cadence.
    You can not design anything in Cadence.

    Or do you mean an outsource design service in Cadence ?

    Use correct terminology .
    Last edited by pancho_hideboo; 29th October 2019 at 09:10.

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