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Voltage drop of on die power gating cells

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volsky

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There are on die power gating cells, connect to VDD or VSS. How about their voltage drop? How dose they affect the circuit timing closure? Can anyone give me some clue?
 

There are on die power gating cells, connect to VDD or VSS. How about their voltage drop? How dose they affect the circuit timing closure? Can anyone give me some clue?

Not sure I understand the question. Are you implying that power gate cells will deliver a derated VDD to the block that they switch off and therefore timing analysis should take that into account?
 

I would think the effect of voltage drop on power switches on timing would be the same as the effects of voltage drop on the interconnects (external and virtual power / ground nets).
 

Not sure I understand the question. Are you implying that power gate cells will deliver a derated VDD to the block that they switch off and therefore timing analysis should take that into account?
I wonder the principle of power switch. Is it a transistor? If so, there should be Drain-Source voltage drop. This would derate VDD to he block that they switch off, and have bad effect on timing and power dissipation.
 

I wonder the principle of power switch. Is it a transistor? If so, there should be Drain-Source voltage drop. This would derate VDD to he block that they switch off, and have bad effect on timing and power dissipation.

Yes, it usually is a big transistor on the header and another big one on the footer. There is a drop, but this usually is well within the characterization range of the standard cells. Say, for instance, your nominal VDD is 1.0V, you will get std cell lib files characterized for 0.9, 0.85, 0.8, etc.
 

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