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There are on die power gating cells, connect to VDD or VSS. How about their voltage drop? How dose they affect the circuit timing closure? Can anyone give me some clue?
I wonder the principle of power switch. Is it a transistor? If so, there should be Drain-Source voltage drop. This would derate VDD to he block that they switch off, and have bad effect on timing and power dissipation.Not sure I understand the question. Are you implying that power gate cells will deliver a derated VDD to the block that they switch off and therefore timing analysis should take that into account?
I wonder the principle of power switch. Is it a transistor? If so, there should be Drain-Source voltage drop. This would derate VDD to he block that they switch off, and have bad effect on timing and power dissipation.