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Loosing data in verilog in case of calculation of variance?

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daskk62

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I am trying to implement variance in vivado 2017.4 using fixed point arithmetic. But so far I observed that, vivado is giving me result without any point after decimal eg. instead of giving 6.56 it is giving 6. And at the end I got a huge difference in the final result, like instead of getting 7.20, answer is coming as 6. View attachment var_data_tb.txtView attachment var_data.txtView attachment value.txt.
The code for the calculation of variance including data is attached. The information about the variance is found in the link below.
https://www.sciencebuddies.org/science-fair-projects/science-fair/variance-and-standard-deviation
 

i see the reading in of 5 data points
i see the calculation of the average (data_mean)
i see the calculation of the sum of squares divided by number of data points (data_diff_sq)
i see the calculation of data_var, but i do not see the subtraction of the mean (data_mean) (as i read equation 5 in the reference you provided)

i do not understand this
//*16'b00000000_00110011;
used
data_mean = data_sum/a;//*16'b00000000_00110011;
and
data_var = data_diff_sq/a;//*16'b00000000_00110011;

i thought // meant what follows is a comment, following the apparent meaning of // based on // scaling factor is 2^-4
 

Looks to me like all the data is right justified and there is nothing being done to set the fixed point to a scaling factor of either 2**-4 or 2**-8 (comment does not match parameter).

As calculations are right justified a 6.56 will be truncated to 6, so it makes sense what you are seeing. You should do some reading on Q formats (i.e. fixed point formats).

- - - Updated - - -

Also you shouldn't be trying to write all your code with initial blocks. This code probably won't even synthesize correctly.

Initial blocks represent the initial value at TIME 0. They will never update after they finish the first time. Synthesis will probably reduce to nothing as the logic is never updated after time 0.

I sometimes wonder where people are getting their Verilog knowledge from, where ever or however they are getting it, isn't right. Personally I just read the book The Verilog Hardware Description Language by Thomas/Moorby way back in the early 90s and never had a problem with writing Verilog code. Perhaps this is because I started by drawing the schematic of the design and then translated it to Verilog. After a month or so I didn't need to do that, since I knew how I should write the code to get the circuit I wanted.
 

//*16'b00000000_00110011; means comment (//), ignoring the line. Subtraction of mean is there. refering to the line data_diff=(datatxt*sf-data_mean*sf) or data_diff=(datatxt-data_mean). Can you tell me the fixed point representation of the code or any manual will be appreciated.

Thank you so much, can you tell me the fixed-point representation of the code or what modifications I need to make in order to get a fixed-point representation of the code.
 

I'll try again, since you seem to have ignored my previous post.

Your data is right justified, e.g.
datatex*sf
datatext = 00000101_00000000
sf = 2**-8 = 1/256 (i.e. right shift by 8)
datatext*sf = 00000000_00000101

once you've done your calculations on these right shifted integers (no Q format used here) you end up doing a division
data_diff_sq/a
which turns your integer into an integer and fractional value, where the fractional part is dropped when assigned to data_var.

Q formats have an integer part and a fractional part, you don't scale them you use them as is. You scale to convert from an integer to a Q format or from Q format back to integer.

If the first data is supposed to be a 5 (decimal) then the Q format is something like Q8.8, i.e. 16-bits with 8 integer bits and 8 fractional bits.

You should read the wiki page on Q format.
 

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