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How to measure the C parasitic (internal capacitance) of an inverter using Spectre ?

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Puppet123

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I want to measure the Reff of an inverter.

I know how to measure the Cgate of the inverter.

But how do I get the Cpar of the inverter (that is-the internal capacitance).

Then use these two values to measure the Reff.

I am using Cadence Spectre - how would I set these simulations up ?
 

Look at the capacitances present in a CMOS inverter. Where are Cpar and Cgate?

inv.PNG
 

Please see attached picture for inverter.

I am looking to measure Cpar = Cw in that picture. Cpar being the parasitic capacitance.

- - - Updated - - -

Cgate is Cint in that picture.
 

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  • InverterCap.png
    InverterCap.png
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Please see attached picture for inverter.
This is not inverter.

I am using Cadence Spectre - how would I set these simulations up ?
Cadence Spectre has no relation to Cpar at all.

Cpar is capacitance of line.
Extract capacitance from layout.
For example, Mentor Calibre, Cadence QRC, etc.
 
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You are right - this is an inverter driving another inverter.

I am looking for Cpar - which is the capacitance of the driving inverters internal capacitances without any load of another inverter. This value changes when the inverter drives another inverter (had a load) so I want the intrinsic value of this internal capacitance unload - and get it by simulation.
 
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This value has to be derived from simulation.

I understand properly - you just dont know the answer.

Also, Cadence Spectre is a simulator. Just letting you know that.
 

I understand properly
No.
You can not understand anything at all.

Also, Cadence Spectre is a simulator.
Just letting you know that.
Cpar has no relation to simulation.
You have no knowledge to talk about simulator.

This value has to be derived from simulation.
No.
You can not understand anything at all.

If there is no physical layout, Cpar is zero since Vout is node.

Surely understand basic things correctly before EDA Tool Play.
This is very true for all your previous posts.
 
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let me play devil's advocate here... I think OP is trying to determine the Cload seen by the first inverter by simulation means. Just a wild guess.
 

From the diagram, Cpar=Cw is parasitic capacitance of the wire (more accurately - parasitic capacitance of the net).

In distributed RC parasitic extraction Cpar may correspond to a large number of individual parasitic capacitances of this net, coupled to other nets and to ground.

This parasitic capacitance is a load for the first inverter, or a part of the load - because the total load is Cpar plus input capacitance of the second inverter.

One way to obtain Cpar is to sum up all coupling capacitances of the signal net.
In principle, one can do this manually, by going through a post-layout netlist, and summing up the coupling capacitances attributed to this net.
For small net, that may be easy.
For reasonable size net, this may be tedious and completely impracticle.

One can write a (not so) simple script to parse the post-layout netlist and find Cpar.
Or one can use specialized EDA tools to do that (and much more).

Or one can write a SPICE (Spectre) deck, and simulate just one net (or a net with its load), to apply an AC signal and measure the admittance - and the imaginary part of admittance, divided by angular frequency, will give you the total load capacitance (Cpar or Cpar + second inverter input capacitance).

Max
 

In principle, one can do this manually,
by going through a post-layout netlist,
..,............................
Or one can use specialized EDA tools to do that (and much more).
Use Cadence QRC or Assura from layout not schematic.

It has no relation to simulator at all.
 
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Parasitic elements (R, C, L, K) have the same relationship with the circuit simulator as design elements - transistors, diodes, etc.
Their characteristics are determined by their structure (width, length, thickness, sheet resistances, doping profiles, etc.), and not by circuit simulator.
You can use circuit simulator to simulate a circuit with design elements only (schematic netlist, or device-only extracted netlist), or with design elements and parasitics (using post-layout netlist), or you can use circuit simulator to analyze interconnects only.

Parasitics are extracted in order to use them in circuit (or in EMIR, timing, etc.) simulators, so saying that they have no relation to simulator is not correct.
 

I agree that circuit simulator cannot be used to do parasitic extraction (calculation of parasitic elements - R, C, etc.) - there are specialized tools for that (parasitic extractors - such as StarRC, QRC, Calibre PEX, etc.).

However, a circuit simulator can be used to simulate (or "measure") effective parasitic characteristics based on post-layout netlist (i.e. netlist that contains design elements and parasitic elements - as extracted by extraction tools) - such as point to point resistance on a net, total and coupling capacitances between nets, etc.
 

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