ptkinzer
Newbie level 6
We're looking at using Vivado for a new Series-7 design, and AXI4-Lite seems like the path of least resistance for our own IP. We're a VHDL house, and the BFM that Xilinx provides in Vivado, VIP, is strictly SystemVerilog.
I've written my own basic BFMs for Avalon-MM and Wishbone Classic, but would rather not have to do this for AXI if I don't have to. I'm new to the AXI world. We use Active-HDL for our testbenches.
My questions are:
- What are VHDL folks using for AXI BFMs these days?
- I found the open-source UVVM, which looks promising, does anyone here use it?
https://github.com/UVVM/UVVM
Thanks,
Paul
I've written my own basic BFMs for Avalon-MM and Wishbone Classic, but would rather not have to do this for AXI if I don't have to. I'm new to the AXI world. We use Active-HDL for our testbenches.
My questions are:
- What are VHDL folks using for AXI BFMs these days?
- I found the open-source UVVM, which looks promising, does anyone here use it?
https://github.com/UVVM/UVVM
Thanks,
Paul