+ Post New Thread
Results 1 to 15 of 15
  1. #1
    Newbie level 5
    Points: 68, Level: 1

    Join Date
    Oct 2019
    Location
    WI, US
    Posts
    8
    Helped
    0 / 0
    Points
    68
    Level
    1

    AXI4 VHDL BFM Options

    We're looking at using Vivado for a new Series-7 design, and AXI4-Lite seems like the path of least resistance for our own IP. We're a VHDL house, and the BFM that Xilinx provides in Vivado, VIP, is strictly SystemVerilog.

    I've written my own basic BFMs for Avalon-MM and Wishbone Classic, but would rather not have to do this for AXI if I don't have to. I'm new to the AXI world. We use Active-HDL for our testbenches.

    My questions are:
    - What are VHDL folks using for AXI BFMs these days?
    - I found the open-source UVVM, which looks promising, does anyone here use it?
    https://github.com/UVVM/UVVM

    Thanks,
    Paul

  2. #2
    Advanced Member level 5
    Points: 38,061, Level: 47
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,896
    Helped
    2026 / 2026
    Points
    38,061
    Level
    47

    Re: AXI4 VHDL BFM Options

    I honestly rolled my own (in VHDL) using OSVVM (for scoreboarding and reporting) because all you can get free online is AXI4s and lite, while I needed full AXI4. AXI4L is just a restricted version of AXI4 but functions the same. My AXI4L entity is just a wrapper around a full AXI4 master BFM. I also use ActiveHDL with a sole VHDL licence and it is now very capable as of 10.5a (after Ive had a load of bugs fixed - and 11.1 will finally offer packages as generics). If you understand that every channel in AXI works identically, you can actually just make a generic source and generic sink procedure (that uses a record of any AXI channel type), you've got half of it working already.

    OSVVM and UVVM offer AXIs and AXI4L BFMs. I have not used these because I dont really like being tied into the framework they use. The BFMs Ive rolled are simple entities that any user can just attach to their testbench and stuff a load of data into (via external names). The cynical view is that they are both made by training companies, and hence non-trivial to encourage people to take their training. But OSVVM was created by Jim Lewis, the main VHDL custodian, and it offers a ton of useful features and works more like a toolbox than a whole framework, and hence I love it.

    https://github.com/OSVVM
    (they have an AXI BFM set aswell).


    1 members found this post helpful.

  3. #3
    Newbie level 5
    Points: 68, Level: 1

    Join Date
    Oct 2019
    Location
    WI, US
    Posts
    8
    Helped
    0 / 0
    Points
    68
    Level
    1

    Re: AXI4 VHDL BFM Options

    Thanks, I'll take a look at OSVVM, looks intriguing. I don't *think* I'll need full AXI, except if I want to drive some Xilinx IP (EMC or VIP, for example). I'm hoping AXI Lite will be sufficient for our rather low throughput needs. The toolbox paradigm is attractive, rather than a framework.

    I expect our designs to be quite small, and not terribly high speed. I hope OSVVM/UVVM aren't overkill. My testbench methodology has been rather home-grown, simple self-checking testbenches that run a series of test cases, each consisting of block setup through configuration registers, waveform generation for the inputs, and output/status monitoring.

    I've asked Xilinx, through our FAE, how to wrap up their VIP with VHDL functions, but so far, their answer is just to use SystemVerilog. (Altera provides a SystemVerilog VIP for Avalon, but *also* provide a VHDL wrapper for use in VHDL testbenches - though I haven't tried it, always used my home-grown Avalon BFM)



    •   AltAdvertisement

        
       

  4. #4
    Advanced Member level 5
    Points: 38,061, Level: 47
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,896
    Helped
    2026 / 2026
    Points
    38,061
    Level
    47

    Re: AXI4 VHDL BFM Options

    Xilinx is all sv now and not providing vhdl models for anything. You're stuffed if you only have avhdl license



  5. #5
    Super Moderator
    Points: 31,891, Level: 43
    ads-ee's Avatar
    Join Date
    Sep 2013
    Location
    USA
    Posts
    7,382
    Helped
    1731 / 1731
    Points
    31,891
    Level
    43

    Re: AXI4 VHDL BFM Options

    Quote Originally Posted by TrickyDicky View Post
    Xilinx is all sv now and not providing vhdl models for anything. You're stuffed if you only have a vhdl license
    That's because Xilinx expects you'll be using Vivado simulator for your simulations, which has been aggressively updating support for SV since they finally officially support it (older versions sometime around 2014-2015 had the -sv switch hidden but you could use it if you wanted to accept the chance of bugs). As Vivado's simulator is mixed mode it doesn't matter if their models are in SV and their libraries/cores have a mixture of VHDL and Verilog.

    Unfortunately both Aldec and Mentor charge everyone extra for a mixed simulation license, even thought that is pretty much the standard environment now days, unless you write all your own cores or only select a core in your preferred language even if it's not the cheapest or the best option for your application. Same goes for any VIP, which can be either found as VHDL or Verilog but typically not both.


    1 members found this post helpful.

  6. #6
    Advanced Member level 5
    Points: 38,061, Level: 47
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,896
    Helped
    2026 / 2026
    Points
    38,061
    Level
    47

    Re: AXI4 VHDL BFM Options

    Quote Originally Posted by ads-ee View Post
    That's because Xilinx expects you'll be using Vivado simulator for your simulations, which has been aggressively updating support for SV since they finally officially support it (older versions sometime around 2014-2015 had the -sv switch hidden but you could use it if you wanted to accept the chance of bugs). As Vivado's simulator is mixed mode it doesn't matter if their models are in SV and their libraries/cores have a mixture of VHDL and Verilog.

    Unfortunately both Aldec and Mentor charge everyone extra for a mixed simulation license, even thought that is pretty much the standard environment now days, unless you write all your own cores or only select a core in your preferred language even if it's not the cheapest or the best option for your application. Same goes for any VIP, which can be either found as VHDL or Verilog but typically not both.
    2019.1 now has some quite good VHDL 2008 support in synthesis (generic packages, generic types and functions as generics). But the simulator is way behind, which seems very odd.
    Xilinx even provide SV with SVA embedded in it (The XPM CDC Block), which is a 3rd paid for licence licence (Xilinx simulator just ignores it). The workaround is to recompile the xilinx libraries removing the SVA (but you'll have to do that yourself). Very Annoying.
    To be honest, most of the Xilinx simulation starts off as a joke - the infamous glbl.v has been around for years, is required and provides a GSR that you should not need in a functional sim. Hooking into it in a VHDL sim is another kludge!


    1 members found this post helpful.

    •   AltAdvertisement

        
       

  7. #7
    Newbie level 5
    Points: 68, Level: 1

    Join Date
    Oct 2019
    Location
    WI, US
    Posts
    8
    Helped
    0 / 0
    Points
    68
    Level
    1

    Re: AXI4 VHDL BFM Options

    Thanks for the discussion, I've been out of active FPGA work for a couple years, doing embedded SW, so am trying to catch up to current tools. Active-HDL doesn't seem much different, but Vivado is a whole new animal, at least compared to ISE and Quartus. We have Active-HDL Plus Edition, I've found in the past that there is always some verilog involved when using IP, so I'm covered for mixed-language simulation. What I haven't yet found is a VHDL interface to the Xilinx SystemVerilog VIP.



    •   AltAdvertisement

        
       

  8. #8
    Advanced Member level 5
    Points: 38,061, Level: 47
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,896
    Helped
    2026 / 2026
    Points
    38,061
    Level
    47

    Re: AXI4 VHDL BFM Options

    The Xilinx SV VIP is pure SV, dont bother trying to use it in a VHDL testbench. Either write a SV testbench or find another BFM.



  9. #9
    Newbie level 5
    Points: 68, Level: 1

    Join Date
    Oct 2019
    Location
    WI, US
    Posts
    8
    Helped
    0 / 0
    Points
    68
    Level
    1

    Re: AXI4 VHDL BFM Options

    I think we'll look for another BFM. What's interesting, though, is that Intel/Altera's Avalon BFM is SV, but provides a VHDL package for use in a VHDL testbench. Seems like it should be possible with VIP.



  10. #10
    Newbie level 5
    Points: 68, Level: 1

    Join Date
    Oct 2019
    Location
    WI, US
    Posts
    8
    Helped
    0 / 0
    Points
    68
    Level
    1

    Re: AXI4 VHDL BFM Options

    It turns out that even the PE multi-language version of Active-HDL (VHDL, Verilog, SV) is incompatible with Xilinx VIP . It supports SV design constructs, but not the advanced verification constructs. Riviera-Pro would be needed, according to Aldec. There are app notes for OSVVM & UVVM, supported in both Active-HDL and Riviera-PRO, so this is encouraging:

    UVVM:
    https://www.aldec.com/en/support/res.../articles/1884

    OSVVM:
    https://www.aldec.com/en/support/res.../articles/1902

    I have not yet tried these.



  11. #11
    Advanced Member level 5
    Points: 38,061, Level: 47
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,896
    Helped
    2026 / 2026
    Points
    38,061
    Level
    47

    Re: AXI4 VHDL BFM Options

    That UVVM article is very gushing an implies that OSVVM doesnt have any reporting. OSVVM has had reporting and alerts for a long time.

    You can get the OSVVM documnentation here:
    https://github.com/OSVVM/OSVVM/tree/master/doc

    AlertLogPackage is the reporting package


    1 members found this post helpful.

  12. #12
    Newbie level 5
    Points: 68, Level: 1

    Join Date
    Oct 2019
    Location
    WI, US
    Posts
    8
    Helped
    0 / 0
    Points
    68
    Level
    1

    Re: AXI4 VHDL BFM Options

    So, I finally have a bit of time to look at OSVVM. I have the some of the AXI4Lite test benches running in Active-HDL. While there's a bunch of documentation for OSVVM, there doesn't seem to be any documentation for the AXI4 BFM portion. There doesn't appear to be a straight-forward way to plug in a synthesizable AXI4Lite compliant slave.



    •   AltAdvertisement

        
       

  13. #13
    Advanced Member level 5
    Points: 38,061, Level: 47
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,896
    Helped
    2026 / 2026
    Points
    38,061
    Level
    47

    Re: AXI4 VHDL BFM Options

    Thats the one thing about OSVVM Ive never really tried to use or felt very comfortable with - the use of resolution functions on custom record types for transactions. Thats probably why it feels alien.
    What was broken with the Xilinx VIP in ActiveHDL? was it the use of SVA? You can re-compile their code in ActiveHDL to remove it with the -na switch to vlog (no assertions). SVA is a separate licence feature in ActiveHDL.

    Code:
    alog -sv2k12 -work <library> -na all <file>
    Afaik, the AXI BFMs are currently more of an example than an official part of OSVVM but I know Jim Lewis wants more inclusion or wants to work on it.

    If you need any help rolling your own - feel free to ask.



  14. #14
    Newbie level 5
    Points: 68, Level: 1

    Join Date
    Oct 2019
    Location
    WI, US
    Posts
    8
    Helped
    0 / 0
    Points
    68
    Level
    1

    Re: AXI4 VHDL BFM Options

    Thanks.

    I've rebuilt the entire set of Xilinx libraries for Active-HDL with the -na all switch. It was easy, once I found the Vivado config_compile_simlib TCL command:

    Code:
    config_compile_simlib -cfgopt {active_hdl.verilog.xpm:-sv2k12 -na all}
    This got me past some SVA usage in the AXI IP, and I've been able to run top-level Active-HDL simulations of IP Integrator designs, including my custom AXI IP and Xilinx AXI IP. My Top level has a custom CPU-to-AXI bridge, so I just use a CPU BFM.

    I haven't tried to use VIP with Active-HDL, this is what Aldec told me when I asked:

    1) Currently the only way to use Xilinx AXI-VIP is to upgrade to our LVT-SV mixed language tool.
    2) Yes, LVT-SV is only available in Riviera-PRO.
    3) Active-HDL only supports System Verilog Design Constructs. The VIP uses SV verification constructs that are not supported in Active-HDL.

    -Paul



  15. #15
    Advanced Member level 5
    Points: 38,061, Level: 47
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,896
    Helped
    2026 / 2026
    Points
    38,061
    Level
    47

    Re: AXI4 VHDL BFM Options

    Interested to know what that Aldec rep is on about, as Active HDL now support UVM (which is basically full on SV). Given AXI-VIP is just SV (not uvm as it works in the free XSIM) I would be surprise if you acutually need LVT_SV (which I think is a riviera-pro licence) or if your vedor rep just wants commision on his sale.

    Going SV is quite a change if you only know VHDL. SV goes full OO, but the techniques can be worth knowing if you want to get full understanding fo protected types in VHDL (basically classes with no inheritance, but used extensively in OSVVM and UVVM).



--[[ ]]--