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  1. #1
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    current mirror typical variation with load

    Hi all. I am desiging a current mirror. If we assume we have a reference current of 10 uA. What is typically the allowed error in a "good design"? In other words, if the design was a cascode current mirror, and the load changes from very small to the maximum load that is allowed by the headroom (for example 1V @100k Ohm). If the current changes from 10 uA to 10.1 (1%) at this range, is it good or bad? I mean only in schmatic before layout?
    Thanks for support.

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  2. #2
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    Re: current mirror typical variation with load

    It is really depending on what you want. If 1% is good for you then no problem. 1% sounds good if you want to use it for not high-performance measurements, it is excellent if you generate bias for internal circuits, and poor if you want to set 1A with 1uA resolution. Normally the loaded condition is the relevant btw, so if it isn't accurate when it is grounded or not used then it can be don't care.
    "Try SCE to AUX." /John Aaron/


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  3. #3
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    Re: current mirror typical variation with load

    Suppose that gain of the transistor in your first column is 100. Try setting a gain of 110 in the second column (reasonable values in real life). Does this cause unacceptable mismatch of 'On' thresholds? Does it cause unacceptable linearity of response?

    In hardware you may need to install a potentiometer adjust or two, to get thresholds to match exactly, and to yield linear response curve.



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