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Bias sequencing card for GaN transistor

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mitta_sathish

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Hi,

I need to have Bias Sequence card for GaN based Power Amplifier.

GaN based device needs sequencing , Gate voltage (-6V to -2V) first and then Drain voltage (Vd) (40 to 62V).


please help me to do this .

REgards,
sathish
 

This can be pretty simple, I have done this as a tiny piece
of T/R element control ASICs decades back.

I'd bet there are many app notes regarding this for GaAs
MMICs which tended to not have internal bias control
(sequencing was built into that function). The difference
would mainly be in the Vgg (slightly more negative for
dGaN) and Vd (much higher voltage switch needed, and
its own drive particulars).

Here's a schematic that worked for a GaAs T/R MMIC,
"back in the day" using 3.3V CMOS (SOI). Using JI you
will have some difficulty operating below ground (and
the only negative supply, is what you're trying to sense
and one that doesn't want a lot of digital switching cr@p
thrown onto it). Device type texts are redacted as this
might tell too much about the foundry, who shall remain
nameless.
 

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-Connect the Load
-Adjust Vgs to permissible min. value
-Adjust Vds to wanted value
-Connect RF Input (RF OFF)
-Connect Vgs @min. and observe no Ids flows
-Connect Vds @nom.
-Adjust Vgs to get Ids quiescent
-Increase RF Input slowly and observe Ids and RF Out simultaneously.
 

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