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Maximum output voltage of operation amplifier with maximum load current

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Junus2012

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Dear friends,

In all of the op-amp design procedure given by any text, the maximum output voltage is designed and defined as the output range where the output transistor are at the boundary of saturation region, therefore for example if we take a simple two stage miller opamp, the maximum VOmax= VDD-VDS(sat)7 and VOmin = VSS+VDS(sat)6.

One can see the output range from the open loop DC transfer (Vin vs Vo), where the output range is the linear range and agrres to the last calculation.

However, These calculation ignores the load current, why ?

What is the simulation setup to run the output voltage range including load affect, I am thinking to connect the op amp in open loop configuration, and make Vo=Vomax by connecting Vin+> Vin-, then I sweep load (current source load) and record the drop of the output voltage, similarly I do Vin-> Vin+ to find the VOmin


Thank you in advance
 

Hi. If I understand you correctly, I assume you mean the output load is much higher (open) resistance than opamp output resistance. So for a capacitive load, you have I= C dV/dt. The maximum output voltage will stay the same but the dV/dt will be limited according to the output current.
Vomax like you said is VDD-VDsat(pmos)
 
Hi. If I understand you correctly, I assume you mean the output load is much higher (open) resistance than opamp output resistance. So for a capacitive load, you have I= C dV/dt. The maximum output voltage will stay the same but the dV/dt will be limited according to the output current.
Vomax like you said is VDD-VDsat(pmos)

Thank you deep_sea for your reply

Actually I was meaning why we consider the small signal current in our op-am design calculation which is not includes the current load
 

ID DC current, id small signal
Now when talking about voltage gain, we calculate vout= id*Rout//RL.
If RL is open, this means you have a full voltage gain because you will multiple id by Rout. Notice that the opamp is basically a "low" frequency "voltage" amplifier. If the whole current passes in the output transistors without a current at the load, then the voltage gain is maximum. If the load has a non negligible output resistance, then the small signal voltage gain will be reduced but the DC current and voltage are not affected. I hope this helps.
 
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