Hi all,
I want to build a 410 GHz high-frequency microstrip patch antenna in the UMC 130nm CMOS process. For this purpose, I have already built the geometry of the patch antenna in HFSS software. But I need a high-frequency switch to control the reconfigurability of the antenna. This means I want to control the phase of the patch antenna using the high-frequency switch. Since HFSS considers any switch as an RLC lump parameter, I need to design a 410GHz transistor switch in Cadence Virtuoso using the UMC 130nm CMOS process.

My question is how do I simulate a transistor and retrieve the equivalent lump RLC circuit of the transistor switch?
I would be highly grateful if anyone points out the steps I need to follow to model a transistor as an RLC lump parameter in Cadence Virtuoso.