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    help please tosimulate this file

    hello
    please can somebody tell me how to simulate this file in quartus 13.1
    i dont know i get just error
    this the mips processor from book design digital of computer architecture here is vhdl file https://files.fm/u/wph4x5ze
    all mudules are in one file i dont know how to do it ?


    thnx

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    Re: help please tosimulate this file

    What do you want to achieve? Quartus is a FPGA synthesis tool, not a simulator. You may use the free Altera Starter Edition of Modelsim shipped with Quartus 13.1

    To simulate the design, you need to write a testbench that provides stimulus signals.



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    Re: help please tosimulate this file

    hello thanks

    yes i simulate with modelsim and active hdl
    but active hdl you can make a block diagram you have all symbols of this file mips

    and i dont use active hdl but i want also in quartus to simulate and to make all symbols from file and to connected together in block diagram from this file

    what do you think sir, is this file for modelsim, if it is, i try i make library to import to quartus but nothing happen

    just one more question? how or what i have to do to simulate in quartus?

    for example do i need to seperate all modules in that file?



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    Re: help please tosimulate this file

    Uh, there's no way I'm clicking on some random shortened link. Especially after checking it...
    Current status
    warning
    This site hosts files that are not commonly downloaded

    The site https://files.fm/u/wph4x5ze contains harmful content, including pages that:

    Contain suspicious or unknown software
    Yeah that makes me ready to click on the link, NOT!

    Quote Originally Posted by michael 1978 View Post
    hello thanks

    yes i simulate with modelsim and active hdl
    but active hdl you can make a block diagram you have all symbols of this file mips

    and i dont use active hdl but i want also in quartus to simulate and to make all symbols from file and to connected together in block diagram from this file

    what do you think sir, is this file for modelsim, if it is, i try i make library to import to quartus but nothing happen

    just one more question? how or what i have to do to simulate in quartus?

    for example do i need to seperate all modules in that file?
    Your questions don't even make sense most of the questions involve doing something with a tool that doesn't even do that something. Like using Active HDL for block diagrams? Or importing libraries to Quartus?

    Quartus - Intel/Altera Synthesis tool converts HDL to gates in Intel FPGA library primitives.
    Modelsim - Intel's simulator packaged with Quartus, used for simulating an HDL design before and after synthesis.
    Active HDL - Aldec's simulator (AFAIK not part of Quartus), an alternative simulator to Modelsim.

    I suspect your English skills are a the main problem with your questions, try running your questions through google translate into English from your primary language. Perhaps that will make your questions more understandable.



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    Re: help please tosimulate this file

    Quote Originally Posted by ads-ee View Post
    Uh, there's no way I'm clicking on some random shortened link. Especially after checking it...

    Yeah that makes me ready to click on the link, NOT!


    Your questions don't even make sense most of the questions involve doing something with a tool that doesn't even do that something. Like using Active HDL for block diagrams? Or importing libraries to Quartus?

    Quartus - Intel/Altera Synthesis tool converts HDL to gates in Intel FPGA library primitives.
    Modelsim - Intel's simulator packaged with Quartus, used for simulating an HDL design before and after synthesis.
    Active HDL - Aldec's simulator (AFAIK not part of Quartus), an alternative simulator to Modelsim.

    I suspect your English skills are a the main problem with your questions, try running your questions through google translate into English from your primary language. Perhaps that will make your questions more understandable.
    good morning

    i try to do the best with google translate!
    sir, i cant come til the analysis and synthesis,i get error!
    yes that is true i want to make quartus fpga library primitives.
    that i want fpga library primitive from that source file mips.vhdl.
    Sorry about my file i just find that link..i dont know ... do you have any address link to put my file online... this file i take from https://booksite.elsevier.com/978012...=9780123944245 file ◾HDL files (updated March 2015).zip file and it is file 07-mipssingle.

    thanks man.



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    Re: help please tosimulate this file

    Quote Originally Posted by michael 1978 View Post
    yes that is true i want to make quartus fpga library primitives.
    that i want fpga library primitive from that source file mips.vhdl.
    I'm not sure that is even possible without knowing how the libraries are installed in the tools, which the only ones who do that are the engineers at the Altera/Intell factory that build the tools.

    That publisher site was fine and I took a look at the files and don't understand why you want to make it a library primitive. I suspect this isn't real goal, but what you think is the way to accomplish something else entirely.

    What is your actual end objective here? Are you actually trying to create a pre-compiled, pre-placed IP block you can use in other designs? There are methods to do this in Xilinx creating synthesized, placed (relative placement) and routed blocks you can then reuse, but I don't know the Quartus tools well enough to tell you exactly how to do it in Intel land.


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    Re: help please tosimulate this file

    Quote Originally Posted by ads-ee View Post
    I'm not sure that is even possible without knowing how the libraries are installed in the tools, which the only ones who do that are the engineers at the Altera/Intell factory that build the tools.

    That publisher site was fine and I took a look at the files and don't understand why you want to make it a library primitive. I suspect this isn't real goal, but what you think is the way to accomplish something else entirely.

    What is your actual end objective here? Are you actually trying to create a pre-compiled, pre-placed IP block you can use in other designs? There are methods to do this in Xilinx creating synthesized, placed (relative placement) and routed blocks you can then reuse, but I don't know the Quartus tools well enough to tell you exactly how to do it in Intel land.
    hi

    no i just want to try add vga and keyboard, and i look for my self easy way to do in that way!
    of one question man i look long time in internet books
    i cant find one book wich explain complete computer with display and keyboard everything connected.
    do you know any book?

    thnx



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