+ Post New Thread
Results 1 to 13 of 13
  1. #1
    Newbie level 3
    Points: 37, Level: 1

    Join Date
    Oct 2019
    Posts
    3
    Helped
    0 / 0
    Points
    37
    Level
    1

    Voltage spikes on the Gate-source of upper H-Bridge MOSFETs (for LLC converter)

    Here is a problem I encountered in the Lab today and would love to hear your thoughts about it.

    I was testing a LLC converter I designed under high voltage (500V) and after couple of test under low power (100kHz, 300ns dead time), upper MOSFETs (SCT3160) of H-bridge got damaged. Both of the damaged MOSFETs had gate and source shorted. I replaced the both MOSFETs with new ones and checked the drain source voltage with a differential probe and saw there were a voltage spike of 30V on each of the upper side MOSFETs. However, there was no visible spikes on the MOSFET gate of lower bridge. This voltage spike is not present when the no voltage is applied to the input terminals of the H-bridge and increases with applied voltage. Since, I am not drawing any current it is surely not due to hard switching of the MOSFETs. Which begs the question what can cause this spikes?

    Here are some information on the design:

    My gate driver schematic for one leg looks like this:
    Click image for larger version. 

Name:	1.PNG 
Views:	18 
Size:	34.1 KB 
ID:	156120
    The upper bridge is supplied from a separate 15V isolated DC-DC converter (SPU02N-15). The schematics for this is shown in attachment.
    Click image for larger version. 

Name:	Unbenannt2.PNG 
Views:	11 
Size:	20.3 KB 
ID:	156117
    I don't know if it helps here is a snapshot of the layout of the MOSFET gate drivers



    Since this is the first time I have undertaken hardware project my knowledge in this field is limited and your kind help is solicited.

  2. #2
    Advanced Member level 5
    Points: 40,054, Level: 48

    Join Date
    Mar 2008
    Location
    USA
    Posts
    6,466
    Helped
    1894 / 1894
    Points
    40,054
    Level
    48

    Re: Voltage spikes on the Gate-source of upper H-Bridge MOSFETs (for LLC converter)

    #1 cause of spikes is stray inductance against a hard
    switched current.

    Whether this is in the driver-gate-source-SW loop or
    the VB-gate-SW loop, is one thing to figure out - is
    the spike driven out the HO because it must follow VB
    or is it that HO, gate are fine w.r.t. SW at the driver,
    but the gate in-the-moment is jacked by inductive
    overshoot on the upper FET source leg inductance?

    Adding 'scope probes can corrupt the measurement
    in high dV/dt activity, adding to the "pull" against the
    common mode dV/dt and injecting currents where
    there were none (or less). This could itself be a
    diagnostic (if you blew up FETs more, or less, when
    poking a particular flying node).

    Speaking of flying nodes, I don't think 2.2uF is very
    good for driving a (say) 2nF Cgg FET, and especially
    not if this fly-cap has poor ESL / ESR. I would at least
    give it the same HF 100nF cap as you see on the
    input supplies. Maybe even more as it's a harsh dV/dt,
    dI/dt environment.


    1 members found this post helpful.

    •   AltAdvertisement

        
       

  3. #3
    Advanced Member level 5
    Points: 11,565, Level: 25

    Join Date
    Aug 2015
    Location
    Melbourne
    Posts
    1,881
    Helped
    695 / 695
    Points
    11,565
    Level
    25

    Re: Voltage spikes on the Gate-source of upper H-Bridge MOSFETs (for LLC converter)

    the spikes are likely a result of your probing - can you post a pic please? if you have too much dead time you may be hard switching the top fets - and yes a 470nF MLCC across the 2u2 is a good idea ...



  4. #4
    Advanced Member level 5
    Points: 20,746, Level: 34
    Achievements:
    7 years registered

    Join Date
    Jan 2011
    Posts
    3,389
    Helped
    1213 / 1213
    Points
    20,746
    Level
    34

    Re: Voltage spikes on the Gate-source of upper H-Bridge MOSFETs (for LLC converter)

    Wait, you see a 30V spike on the Vds of the upper FETs, or their Vgs?

    Your layout definitely has excess inductance in the gate drive loops. But I don't think that alone can explain 30V showing up on the gate...

    I'm betting the 30V spike you're seeing is due to bad probing, and the failure lies elsewhere, like cross conduction or excessive switching losses.



    •   AltAdvertisement

        
       

  5. #5
    Advanced Member level 5
    Points: 11,565, Level: 25

    Join Date
    Aug 2015
    Location
    Melbourne
    Posts
    1,881
    Helped
    695 / 695
    Points
    11,565
    Level
    25

    Re: Voltage spikes on the Gate-source of upper H-Bridge MOSFETs (for LLC converter)

    light load ( at usually high frequency ) is one of the danger spots for LLC if the dead time is not perfect ...

    - - - Updated - - -

    a good check on your diff probe is to put both probes on the source of the upper device ( i.e. shorted together on the source ) - a really good diff probe will show a flat line - a cheapy one will show the 30V spike you mentioned earlier ....


    1 members found this post helpful.

    •   AltAdvertisement

        
       

  6. #6
    Newbie level 3
    Points: 37, Level: 1

    Join Date
    Oct 2019
    Posts
    3
    Helped
    0 / 0
    Points
    37
    Level
    1

    Re: Voltage spikes on the Gate-source of upper H-Bridge MOSFETs (for LLC converter)

    Quote Originally Posted by dick_freebird View Post
    #1 cause of spikes is stray inductance against a hard
    switched current.

    Whether this is in the driver-gate-source-SW loop or
    the VB-gate-SW loop, is one thing to figure out - is
    the spike driven out the HO because it must follow VB
    or is it that HO, gate are fine w.r.t. SW at the driver,
    but the gate in-the-moment is jacked by inductive
    overshoot on the upper FET source leg inductance?

    Adding 'scope probes can corrupt the measurement
    in high dV/dt activity, adding to the "pull" against the
    common mode dV/dt and injecting currents where
    there were none (or less). This could itself be a
    diagnostic (if you blew up FETs more, or less, when
    poking a particular flying node).

    Speaking of flying nodes, I don't think 2.2uF is very
    good for driving a (say) 2nF Cgg FET, and especially
    not if this fly-cap has poor ESL / ESR. I would at least
    give it the same HF 100nF cap as you see on the
    input supplies. Maybe even more as it's a harsh dV/dt,
    dI/dt environment.
    Quote Originally Posted by Easy peasy View Post
    the spikes are likely a result of your probing - can you post a pic please? if you have too much dead time you may be hard switching the top fets - and yes a 470nF MLCC across the 2u2 is a good idea ...

    Thank you very much for your reply. Its interesting to hear your point of view.
    Here is a pic How my Mosfet H Bridge looks like ( they are mounted on a heat sink) and
    Click image for larger version. 

Name:	without probe.jpeg 
Views:	0 
Size:	166.5 KB 
ID:	156139


    here is how I connected to take the measurement of V_GS of Upper and lower MOSFET of the H-Bridge.

    Click image for larger version. 

Name:	With probe.jpeg 
Views:	2 
Size:	157.3 KB 
ID:	156138

    Bellow are also two snaps of the osci Gate to source voltage measurement of lower and upper bridge.
    Click image for larger version. 

Name:	scope_10.png 
Views:	2 
Size:	42.4 KB 
ID:	156140Click image for larger version. 

Name:	scope_9.png 
Views:	1 
Size:	29.4 KB 
ID:	156141

    I managed to damage one more upper MOSFET during taking measurement today. I am beginning to think the way I am probing is the root of the problem. How do you suggest should I probe to find out if switching is taking place or not without ideally not damaging the MOSFETs? Is it safe to use the above probe setup when no High voltage is applied to the bridge? Would be awesome if you can suggest some reading material on this

    Regarding your other suggestion I wil try to replace the 2,2uF between VB and VS with a 100nF MLCC.

    One more thing I would like to bring to your attention is the boot strap arrangement for the upper MOSFETs. I avoided the boot-strap diode by connecting VB to + of 15V isolated DC-DC and -ve end to switching node. I have used no bootstrap diode in between them. Do you think this could cause potential problem? Additionally I used a 10k resistance between gate node and switch node to make sure gate voltage is not floating? Is that a good practice?


    Quote Originally Posted by Easy peasy View Post
    the spikes are likely a result of your probing - can you post a pic please? if you have too much dead time you may be hard switching the top fets - and yes a 470nF MLCC across the 2u2 is a good idea ...
    I have attached some additional photos for your kind perusal. Looking forward to your inputs



  7. #7
    Super Moderator
    Points: 261,221, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    45,636
    Helped
    13878 / 13878
    Points
    261,221
    Level
    100

    Re: Voltage spikes on the Gate-source of upper H-Bridge MOSFETs (for LLC converter)

    We are curious to see the result of the common mode test suggested by Easy peasy.



  8. #8
    Advanced Member level 3
    Points: 6,174, Level: 18

    Join Date
    Feb 2014
    Posts
    888
    Helped
    292 / 292
    Points
    6,174
    Level
    18

    Re: Voltage spikes on the Gate-source of upper H-Bridge MOSFETs (for LLC converter)

    Quote Originally Posted by Neelsama View Post
    One more thing I would like to bring to your attention is the boot strap arrangement for the upper MOSFETs. I avoided the boot-strap diode by connecting VB to + of 15V isolated DC-DC and -ve end to switching node. I have used no bootstrap diode in between them. Do you think this could cause potential problem? Additionally I used a 10k resistance between gate node and switch node to make sure gate voltage is not floating? Is that a good practice?
    I don't see problems with the gate drive. You need either an isolated supply or bootstrap. If you have one you don't need the other. The 10k might be a risk if bootstrapped (it drains the bootstrap cap) but not with a proper supply on the gate drive.



  9. #9
    Advanced Member level 5
    Points: 11,565, Level: 25

    Join Date
    Aug 2015
    Location
    Melbourne
    Posts
    1,881
    Helped
    695 / 695
    Points
    11,565
    Level
    25

    Re: Voltage spikes on the Gate-source of upper H-Bridge MOSFETs (for LLC converter)

    ADD 470nF to the 2.2uF ...!



  10. #10
    Advanced Member level 5
    Points: 40,054, Level: 48

    Join Date
    Mar 2008
    Location
    USA
    Posts
    6,466
    Helped
    1894 / 1894
    Points
    40,054
    Level
    48

    Re: Voltage spikes on the Gate-source of upper H-Bridge MOSFETs (for LLC converter)

    Quote Originally Posted by Neelsama View Post
    One more thing I would like to bring to your attention is the boot strap arrangement for the upper MOSFETs. I avoided the boot-strap diode by connecting VB to + of 15V isolated DC-DC and -ve end to switching node. I have used no bootstrap diode in between them. Do you think this could cause potential problem? Additionally I used a 10k resistance between gate node and switch node to make sure gate voltage is not floating? Is that a good practice?
    The "flying supply" could be a bad actor if it has any common
    mode sensitivity (dV/dt, w.r.t. Earth, might push on the
    set voltage, could be overshoots, etc.). There are gate drive
    DC-DC parts and modules meant for high dV/dt applications,
    so presumably there are others that make these products a
    better idea....

    Just one of the things already suggested to probe, and see.

    - - - Updated - - -

    Quote Originally Posted by Neelsama View Post
    here is how I connected to take the measurement of V_GS of Upper and lower MOSFET of the H-Bridge.
    Click image for larger version. 

Name:	With probe.jpeg 
Views:	2 
Size:	157.3 KB 
ID:	156138
    With that clip-lead arrangement you have a large "pickup
    loop" inherent to the probe, and will see ambient magnetic
    field stepping on the electrical waveform.

    You might at least co-bundle the red/black clips minimizing
    the loop area, with one eye on the 'scope to see how any
    artifacts may change (or hopefullly go away, although this
    has not to do with the actual burning of FETs most likely -
    still you'd like to be homing in on the real problem, not
    chasing ghosts).

    Open cores are really bad about "spraying" magnetic field.
    Pot cores (closed magnetic path) are nicer neighbors.



  11. #11
    Advanced Member level 5
    Points: 11,565, Level: 25

    Join Date
    Aug 2015
    Location
    Melbourne
    Posts
    1,881
    Helped
    695 / 695
    Points
    11,565
    Level
    25

    Re: Voltage spikes on the Gate-source of upper H-Bridge MOSFETs (for LLC converter)

    you should put a common mode choke ( size commensurate with current flowing ) right at the upper gate drive on the isolated DC as it comes in - this will stop all the connected stuff flapping up and down at high volts at switching frequency .... one on each high side device



  12. #12
    Newbie level 3
    Points: 37, Level: 1

    Join Date
    Oct 2019
    Posts
    3
    Helped
    0 / 0
    Points
    37
    Level
    1

    Re: Voltage spikes on the Gate-source of upper H-Bridge MOSFETs (for LLC converter)

    Thanks for your feedback. I am waiting to receive the new FETs from the supplier and try your suggestions out. In germany everything takes time :)
    I will keep you posted about further developments.

    Quote Originally Posted by Easy peasy View Post
    you should put a common mode choke ( size commensurate with current flowing ) right at the upper gate drive on the isolated DC as it comes in - this will stop all the connected stuff flapping up and down at high volts at switching frequency .... one on each high side device
    I will give it a try. I found this one in my lab:
    https://katalog.we-online.de/pbs/dat...7448013501.pdf and has around 2x0.5 mH inductance? Will this suffice?

    Once more question regarding adding a 470nF in parallel to 2,2uF. I really don't have a pad free to put them together. What could be alternative to your opinion? I was thinking of replacing a 100nF MLCC to 2,2uF.

    Thank you in advance!



    •   AltAdvertisement

        
       

  13. #13
    Advanced Member level 5
    Points: 40,054, Level: 48

    Join Date
    Mar 2008
    Location
    USA
    Posts
    6,466
    Helped
    1894 / 1894
    Points
    40,054
    Level
    48

    Re: Voltage spikes on the Gate-source of upper H-Bridge MOSFETs (for LLC converter)

    It's not about C alone, it's about whether the C in series
    with its R, L internal "baggage" can jump up in time to
    quench common mode excursion driven spikes. More C
    helps little if its ESL, ESR are too high.

    For experiments, you can stack caps on each other. But
    if the real problem is a bad route (large loop, skinny trace,
    lonely via) there may be no such thing as "good enough"
    at the component level.

    A "RF" 100nF cap will be better than another "Audio" 2.2uF
    most likely. Bargain bin caps are anybody's guess.



--[[ ]]--