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    Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    I am designing a very basic gate (inverter) in custom designer using SAED PDK90nm. I am able to create the schematics and layouts and generate Parasitics. When I run the simulation on testbench circuit (using schematic only) it works fine, however, when I run the same testbench with parasitics it does not work. It gives warning and Extra terminal VDD and VSS found in symbol not found in starrc.
    I am attaching the waveforms for both the simulations. The top 4 are for the schematic and it does not show the vss option. however in post-LPE the vss has the same waveform as input.
    net5: VDD
    net7: Input signal
    out : output signal
    0: ground
    i haven't defined any net as VSS in test bench circuit.

    I have spent two days to figure out what is the problem but unable to find on internet.

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  2. #2
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    Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    Did you forget to put text labels / ports "VSS" and "VDD" on your layout, on the corresponding nets metal shapes?



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    Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    Quote Originally Posted by timof View Post
    Did you forget to put text labels / ports "VSS" and "VDD" on your layout, on the corresponding nets metal shapes?
    yes, I did put text labels using "M1PIN". All the four labels i.e., VDD, VSS, INV_IN and INV_OUT. The Layout VS schematics is passed without any errors.



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    Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    It's hard to tell from the snapshot you provided, what's wrong.

    What flow are you using?
    Calibre LVS / DRC then StarRC for extraction?

    Can you check if you have nets VDD and VSS on .SUBCKT line in DSPF file?
    (DSPF file is a standard output from extraction tools - a post-layout netlist, in text format, you can see easily and directly all the nets, ports, etc. in the extracted netlist, unlike in extracted view).



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    Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    extraction tools have some expectations regarding VDD/VSS pins and how they should be named. it is possible the tool is expecting vdd! and you called VDD, or whatever other combination of. check your extraction scripts.
    Really, I am not Sam.



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    Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    If LVS is clean, this means 1:1 correspondence between schematic and layout, and net names are matched, so VDD / VSS should be the correct net names.

    Parasitic extraction tools are very weakly affected by net types (power, signal, etc.).
    There are commands in extraction tools telling not to extract power nets - because often, people do not extract power nets since they may be huge (and can make simulation of post-layout netlist impractical, too slow).
    Power nets are listed in command file for extraction tool, while the user can manually defined these names - usually they are automatically passed from LVS by script "gluing" together the whole flow.



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    Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    Quote Originally Posted by timof View Post
    It's hard to tell from the snapshot you provided, what's wrong.

    What flow are you using?
    Calibre LVS / DRC then StarRC for extraction?

    Can you check if you have nets VDD and VSS on .SUBCKT line in DSPF file?
    (DSPF file is a standard output from extraction tools - a post-layout netlist, in text format, you can see easily and directly all the nets, ports, etc. in the extracted netlist, unlike in extracted view).
    I am using Synopsys Custom Designer. I tried to search the using "DSPF" in my working directory. only files that comes up with this search are the OA2DSFP.tech files in Lstarrc.lpe folders and they contain many arguments and one on of them is "-ground_node_name VSS", however they do not contain any .subckt command.
    I have found netlist in the LVS folder that is generated after LVS test and it contains the following:
    "
    ************************************************** ******************************
    * Library : CAN_library
    * Cell : inverter
    * View : schematic
    * View Search List : auCdl schematic symbol
    * View Stop List : auCdl
    ************************************************** ******************************
    .subckt inverter INV_IN INV_OUT VDD VSS
    *.PININFO INV_IN:I INV_OUT:O VDD:I VSS:I
    MM0 INV_OUT INV_IN VDD VDD p12 w=0.5u l=0.1u nf=1.0 m=1
    MM1 INV_OUT INV_IN VSS VSS n12 w=0.25u l=0.1u nf=1.0 m=1
    .ends inverter"
    I have tried to open as many files i could and i have found power_nets file. It just contains 2 words, "VDD VSS".



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    Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    Quote Originally Posted by ThisIsNotSam View Post
    extraction tools have some expectations regarding VDD/VSS pins and how they should be named. it is possible the tool is expecting vdd! and you called VDD, or whatever other combination of. check your extraction scripts.
    I am a novice in this. by the extraction script you are referring to .tcl file and then running it on console. I am using GUI following the guide from following link:
    https://github.com/sheldonucr/ucr-ee...ee/master/lab1

    I have followed each and every step as it is described in it.



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    Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    In lab3 (parasitic extraction), Fig. 6 - select "Format" to be "SPF" (or "DSPF"), if it's available - and you will get a DSPF file format - a simple text file format for post-layout netlist.
    It's content is (almost) identical to OA format, but OA is binary, and DSPF file text, so you can see all the information easily.



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    Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    Quote Originally Posted by timof View Post
    In lab3 (parasitic extraction), Fig. 6 - select "Format" to be "SPF" (or "DSPF"), if it's available - and you will get a DSPF file format - a simple text file format for post-layout netlist.
    It's content is (almost) identical to OA format, but OA is binary, and DSPF file text, so you can see all the information easily.
    Here is the result of that SPF file. It contains the VDD and VSS.
    Code:
    "*
    *|DSPF 1.3
    *|DESIGN inverter
    *|DATE "Tue Oct 22 23:50:15 2019"
    *|VENDOR "Synopsys"
    *|PROGRAM "StarRC"
    *|VERSION "L-2016.06-SP3"
    *|DIVIDER |
    *|DELIMITER :
    **FORMAT SPF
    *
    
    ** COMMENTS
    
    ** OPERATING_TEMPERATURE 25
    ** GLOBAL_TEMPERATURE 25
    ** TCAD_GRD_FILE /hdd1/Ibtesam/Custom_designer/SAED_PDK90nm/starrcxt/saed90nm.nxtgrd
    **   TCAD_TIME_STAMP Mon Mar 21 07:56:03 2016
    **   TCADGRD_VERSION 80
    
    
    .SUBCKT inverter VDD VIN VOUT VSS
    
    *|GROUND_NET VSS
    
    *LAYER_MAP.................................."



  11. #11
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    Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    Good, the .SUBCKT statement looks good.
    You can also check *|NET section for nets VDD and VSS, to make sure these nets are extracted correctly - and you can then assume that the extraction went though correctly.

    If so - the problem is not with the extraction, but with how you use extracted netlist further up the circuit hierarchy.
    Check your test bench, hierarchy editor, etc. - whatever you use to define your test bench, where you instantiate the extracted netlist.



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    Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    Quote Originally Posted by timof View Post
    Good, the .SUBCKT statement looks good.
    You can also check *|NET section for nets VDD and VSS, to make sure these nets are extracted correctly - and you can then assume that the extraction went though correctly.

    If so - the problem is not with the extraction, but with how you use extracted netlist further up the circuit hierarchy.
    Check your test bench, hierarchy editor, etc. - whatever you use to define your test bench, where you instantiate the extracted netlist.
    I checked *|Net section and i found the following code:
    "
    Code:
    *|NET VIN 0.000819726PF
    *|I (MM0:GATE MM0 GATE I 5e-17 -3.79 4.29) // $llx=-3.79 $lly=4.29 $urx=-3.79 $ury=4.29 $lvl=30
    *|I (MM1:GATE MM1 GATE I 2.5e-17 -3.79 2.16) // $llx=-3.79 $lly=2.16 $urx=-3.79 $ury=2.16 $lvl=29
    *|P (VIN B 0 -4.105 3.085) // $llx=-4.11 $lly=3.015 $urx=-4.1 $ury=3.155 $lvl=82
    *|S (VIN:1 -3.7975 3.085) // $llx=-3.855 $lly=3.015 $urx=-3.74 $ury=3.155 $lvl=44
    *|S (VIN:2 -4.34 3.085) // $llx=-4.34 $lly=3.015 $urx=-4.34 $ury=3.155 $lvl=44
    Cg3_1 MM0:GATE VSS 4.51691e-16
    Cg3_2 VIN:2 VSS 7.84798e-17
    R3_1 MM0:GATE VIN:1 8 $a=0.0169 $lvl=67
    R3_2 MM0:GATE MM1:GATE 0.001 $l=2.13 $w=10 $lvl=29
    R3_3 VIN:1 VIN 0.197679 $l=0.3075 $w=0.14 $lvl=44
    R3_4 VIN:2 VIN 0.151072 $l=0.235 $w=0.14 $lvl=44
    
    *|NET VOUT 0.000979819PF
    *|I (MM0:DRN MM0 DRN B 0 -3.74 4.29) // $llx=-3.74 $lly=4.29 $urx=-3.74 $ury=4.29 $lvl=5
    *|I (MM1:DRN MM1 DRN B 0 -3.74 2.16) // $llx=-3.74 $lly=2.16 $urx=-3.74 $ury=2.16 $lvl=4
    *|P (VOUT B 0 -3.52 2.85) // $llx=-3.59 $lly=2.845 $urx=-3.45 $ury=2.855 $lvl=82
    *|S (VOUT:1 -3.52 4.4775) // $llx=-3.59 $lly=4.42 $urx=-3.45 $ury=4.535 $lvl=44
    *|S (VOUT:2 -3.52 4.16) // $llx=-3.59 $lly=4.16 $urx=-3.45 $ury=4.16 $lvl=44
    *|S (VOUT:3 -3.52 2.1025) // $llx=-3.59 $lly=2.045 $urx=-3.45 $ury=2.16 $lvl=44
    C4_3 MM0:DRN MM0:GATE 1.44505e-16
    C4_4 MM0:DRN VIN:2 1.34042e-19
    Cg4_5 MM0:DRN VSS 2.73739e-16
    C4_6 MM1:DRN MM0:GATE 7.74372e-17
    C4_7 MM1:DRN VIN:2 1.03982e-19
    Cg4_8 MM1:DRN VSS 1.68193e-16
    C4_9 VOUT:3 MM0:GATE 2.21731e-17
    C4_10 VOUT:3 VIN:2 4.52021e-17
    Cg4_11 VOUT:3 VSS 2.48332e-16
    R4_5 MM0:DRN VOUT:1 10 $a=0.0169 $lvl=66
    R4_6 MM0:DRN VOUT:2 10 $a=0.0169 $lvl=66
    R4_7 VOUT:1 VOUT:2 0.204107 $l=0.3175 $w=0.14 $lvl=44
    R4_8 VOUT:2 VOUT 0.842144 $l=1.31 $w=0.14 $lvl=44
    R4_9 MM1:DRN VOUT:3 10 $a=0.0169 $lvl=66
    R4_10 VOUT:3 VOUT 0.480536 $l=0.7475 $w=0.14 $lvl=44
    
    *|NET ln_N7 0PF
    
    *|NET ln_N8 0PF
    
    *
    * Instance Section
    *
    XMM0 MM0:DRN MM0:GATE VDD VDD p12 l=0.1u nf=1 w=0.5u
    XMM1 MM1:DRN MM1:GATE VSS VSS n12 l=0.1u nf=1 w=0.25u
    
    .ENDS"
    There isn't any *|NET VDD or VSS.
    Last edited by KlausST; 23rd October 2019 at 07:18. Reason: added code tags



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    Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    This might be a problem.
    This DSPF file is valid, but nets VSS and VDD extracted as ideal nets - meaning they are represented as one node, with no parasitic resistors.
    I suspect the command in StarRC command file to extract power nets is set to NO or something like that.
    There should also be a command in this command file that declares nets VSS and VDD as power nets.

    I recommend to set extraction of the power nets to YES, rerun the extraction, and try to use that file for your circuit simulations.

    However, if DSPF file with ideal nets VSS and VDD was giving you an error, then a DSPF file with RC extracted nets VSS and VDD might give the same error.
    So the problem may be somewhere else...


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    Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    Thanks to all who guided me. I am able to resolve the issue and get the right simulation results. The workaround, which resolved the issue for me, is to manually define the VSS and VDD terminal in starrc Design.
    For the people who are like me, a novice and having this problem, you can open the starrc circuit and go to edit-->>PIN-->>Define Terminal. And the following screen will open. Here, you can add the Terminal name against the net as shown and it will resolve the issue for extra terminals found in symbol and not in starrc.
    Click image for larger version. 

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