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    ADC output bit rate and PCB layout

    Hi,

    I am considering AD9257 ADC for my application. The ADC chip is octal which means 8 ADC on chip. The resolution is 14 bits and sampling rate is 65 MSPS. Each channel has serial LVDS output. There is a statement on the first page of the datasheet which reads.

    "Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 455 MHz and supports double data rate (DDR) operation."

    I guess the differential output means that positive data DA+ and negative data DA- from channel A are just inverted in polarity otherwise they are same, right ? and the double data rate sampling means that it is possible to sample at both edges, right ? which means that (65 x 14) /2 = 455 MHz is the data bit clock to FPGA, right ? and the PCB layout has to be in accordance with 455 MHz, and not 910 MHz, right ?

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    Re: ADC output bit rate and PCB layout

    That seems correct.



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    Re: ADC output bit rate and PCB layout

    Hi,

    I guess it is ok to sample the ADC data at both positive and negative edges in FPGA, right ? Do the FPGA or ZYNQ have LVDS I/O to take the data in at 455 MHz ? How about the layout requirement ? What do I need to take more in to consideration ?



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    Re: ADC output bit rate and PCB layout

    Series 7 is specified for 950 MBPS DDR LVDS speed, 910 MBPS has little margin. It's suggested to use digital phase alignment to adjust the receiver timing.

    DCO and FCO must be sent to the FPGA along with the eight data lanes, DCO to a dedicated clock input. Alternatively use FCO only and derive data clock by a PLL.

    Series 7 provides internal differential termination for LVDS inputs. Just design proper 100 ohm differential pairs between ADC outputs and FPGA.



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    Re: ADC output bit rate and PCB layout

    "Series 7 is specified for 950 MBPS DDR LVDS speed, 910 MBPS has little margin. It's suggested to use digital phase alignment to adjust the receiver timing."

    I guess the effective DCO will be 455 MHz, not 910 MHz, right ? because of double data rate which is sampling on both edges positive and negative. So the margin to Series 7 950 MBPS DDR LVDS speed is more then double ?



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    Re: ADC output bit rate and PCB layout

    Hi,

    Since you have two data per clock period (one per edge): DCO of 455MHz gives 910MBPS.
    --> low margin.

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



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    Re: ADC output bit rate and PCB layout

    475 MBPS SDR and 950 MBPS DDR, why not read the datasheet yourself?



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