+ Post New Thread
Results 1 to 5 of 5
  1. #1
    Newbie level 6
    Points: 168, Level: 2

    Join Date
    Mar 2019
    Posts
    11
    Helped
    0 / 0
    Points
    168
    Level
    2

    Resistor Layout - Guard Ring

    Hi all!
    I am using an rphripoly resistor in TSMC 0.18um pdk. Should I use nwell guardring or psub guard ring? Why?
    Thanks!

    •   AltAdvertisement

        
       

  2. #2
    Advanced Member level 5
    Points: 40,076, Level: 48

    Join Date
    Mar 2008
    Location
    USA
    Posts
    6,470
    Helped
    1895 / 1895
    Points
    40,076
    Level
    48

    Re: Resistor Layout - Guard Ring

    Poly resistor has no substrate contact so there's no need
    for extra isolation measures for leakage. -Maybe- if you
    are extremely sensitive to substrate noise, but even that
    is pretty unlikely outside of RF circuits, parasitic C will be
    pretty small if the poly is over field oxide.


    1 members found this post helpful.

    •   AltAdvertisement

        
       

  3. #3
    Advanced Member level 2
    Points: 5,619, Level: 17
    Achievements:
    7 years registered

    Join Date
    Feb 2008
    Posts
    549
    Helped
    181 / 181
    Points
    5,619
    Level
    17

    Re: Resistor Layout - Guard Ring

    In a three-terminal resistor element, the first and second terminals are connected to the resistor body, and conduct a DC current, while the third one is the "substrate" terminal, describing capacitive coupling between the resistor body and the well under the resistor. Conceptually, this third terminal is like a gate in a MOSFET, but in resistors, usually, their resistance does not depend on the voltage between the resistor body and the well.

    I do not think that the capacitance of the resistor, in its compact model, depend on whether it is nwell or pwell or psubstrate underneath.

    A thing to consider is what net you prefer that resistor body to substrate capacitance be connected to, to VSS or VDD.

    I would suggest to check if the third terminal / instance pin is connected to R network of the VSS/VDD net, or directly shorted to the VSS/VDD port (if AC effects are important in this circuit).

    Another option is to leave the well floating, under the resistor - this will reduce the capacitance (resistor capacitance to substrate will be in series with p-n junction between nwell and psub), but will make its potential undefined (floating) - sometimes, this may be a very bad thing, but sometimes - not.



    •   AltAdvertisement

        
       

  4. #4
    Advanced Member level 5
    Points: 40,076, Level: 48

    Join Date
    Mar 2008
    Location
    USA
    Posts
    6,470
    Helped
    1895 / 1895
    Points
    40,076
    Level
    48

    Re: Resistor Layout - Guard Ring

    If you were really keen on noise control you might put a
    well under it and then that feature would want its usual
    subfeatures and so on. Nwell does not have to be VDD-
    biased, it could be ground pin tied or anywhere in
    between.

    But in any case the guardring would have nothing to do
    with the poly per se. It's a bulk silicon thing.



  5. #5
    Newbie level 1
    Points: 201, Level: 2

    Join Date
    Oct 2018
    Posts
    1
    Helped
    0 / 0
    Points
    201
    Level
    2

    Re: Resistor Layout - Guard Ring

    Quote Originally Posted by big_fudge98 View Post
    Hi all!
    I am using an rphripoly resistor in TSMC 0.18um pdk. Should I use nwell guardring or psub guard ring? Why?
    Thanks!
    As a layout engineer, it depends on the resistor you use. If it has 3 pin outs in schematic, and if you have enough area in your layout, place them under n-well due to noise immunity. It will reduce the noise that resistor creates to get into substrate. You can connect to that n-well any potential other than psub.

    Overall, it's highly specific to circuit requirement. You can put on psub guard ring as well, which will help other components around your resistor be affected by less noise than without a ring.



--[[ ]]--