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    Update .mif file without compiling (Quartus Prime) using TCL

    Hello,

    As the title states I want to pdate a .mif file without the need of compiling each time. Searching I found this intel link

    Here it says that using this I should be able to do what i want:
    Code:
    quartus_cdb --update_mif <project name> 
    quartus_asm <project name>
    So I write the following TCL code:

    Code:
    proc tdc_mif_update {} {
    	
    	set project_name [ get_global_assignment -name TOP_LEVEL_ENTITY ]
    	set family [ get_global_assignment -name FAMILY ]
    	set device [ get_global_assignment -name DEVICE ]
    
    	exec quartus_cdb --update_mif $project_name
    	exec quartus_asm $project_name
    	
    	puts "SiUB (INFO): .mif file updated"}
    When I tried to execute it, it says:
    Code:
    Error:Error (39003): Run Analysis and Synthesis (quartus_map) with revision "magi_fw" for --rev option before running Compiler Database Interface (quartus_cdb)
    And now my real problem, I tried to add quartus_map but it's always giving me errors, the last one is this one:
    Code:
    Error:Error (12007): Top-level design entity "magi_fw" is undefined
    This is the code I added:
    Code:
    set family [ get_global_assignment -name FAMILY ]
    set device [ get_global_assignment -name DEVICE ]
    
    exec quartus_map $project_name --rev=$project_name --family=$family --part=$device
    And the full error message:
    Code:
    Error:Info: Command: quartus_map magi_fw --rev=magi_fw --family="MAX 10" --part=10M25DAF484I7G
    Error:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
    Error:Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
    Error:Error (12007): Top-level design entity "magi_fw" is undefined
    Error:Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning
    Error:    Error: Peak virtual memory: 566 megabytes
    Error:    Error: Processing ended: Tue Oct 15 20:55:08 2019
    Error:    Error: Elapsed time: 00:00:11
    Error:    Error: Total CPU time (on all processors): 00:00:01
    Error:child process exited abnormally
    Error:    while executing
    Error:"exec quartus_map $project_name --rev=$project_name --family=$family --part=$device"
    Error:    (procedure "tdc_mif_update" line 8)
    Error:    invoked from within
    Error:"tdc_mif_update"
    I don't have almost any experience with TCL and with scripting for FPGAs in general.

    Thanks.

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  2. #2
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    Re: Update .mif file without compiling (Quartus Prime) using TCL

    If you don't know Tcl then you should have probably used the third option which involves using the GUI (like most non-Tcl users do) and just updating the mif and recompiling (as nothing other than the mif changes it won't do anything but update the memory and generate a new programming file.



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  3. #3
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    Re: Update .mif file without compiling (Quartus Prime) using TCL

    Quote Originally Posted by ads-ee View Post
    If you don't know Tcl then you should have probably used the third option which involves using the GUI (like most non-Tcl users do) and just updating the mif and recompiling (as nothing other than the mif changes it won't do anything but update the memory and generate a new programming file.
    But I'm trying to learn. I don't think that I'm that far away from doing it correctly.



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  4. #4
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    Re: Update .mif file without compiling (Quartus Prime) using TCL

    Quote Originally Posted by Humusk View Post
    But I'm trying to learn. I don't think that I'm that far away from doing it correctly.
    I gave up trying to learn about scripting FPGA tools, every time I've learned how to do it on version a.b.c they've changed things for version a.b.d and the script no longer works. Dealt with that way too many times.

    I now usually just put everything into the gui and then generate a script for the build and run that instead of writing my own hand written one.

    The tools vendors should learn how user want to script the flow instead of coming up with something annoying. It seems like the developers have no clue I want my code is a specific location and don't want it in their ridiculous managed area buried in 50 levels of directories, which I now have to commit to source control. Seriously the developers are software engineers aren't they the ones that developed the entire concept of source control!?

    Sorry about ranting, but I'd like the current design I'm working on to be scripted, but the tools I'm using are too broken to work properly with their silly schematic block design and separate HDL portions of the design and script it all.



  5. #5
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    Re: Update .mif file without compiling (Quartus Prime) using TCL

    Yeah I come to realise that. The scripting for FPGA is unecesarilly difficult and messy. I've tried to use the GUI but it seems that the .mif files doesn't update correctly (the system don't give any error), I also fixed the script, the problem was that the script file wasn't in the project folder, but it doesn't correctly update. Anyway, thanks for the tips.



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    Re: Update .mif file without compiling (Quartus Prime) using TCL

    Quote Originally Posted by Humusk View Post
    Yeah I come to realise that. The scripting for FPGA is unecesarilly difficult and messy.
    Used to be extraordinarily easy back in the beginning of FPGAs. Used to be Xilinx Foundation tools had no scripting support just a bunch of .exe files you had to run from the command line. I used a make file and all was good, didn't matter if the version of the tools changed, you might have to modify a command line switch or such but nothing that difficult to deal with. You could put your files where ever you pleased and didn't have to deal with the tools sticking everything in some horrible directory structure that would break your OS (windows stupid 260 character limit).

    Ah those were the days. The ASIC tools vendors still seem to understand that engineers want to script their flow. FPGA vendors seem to think we only know how to use a GUI (hmm, maybe there is some truth in that as I'm an old dude ).



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