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  1. #1
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    Output of Nand Sequential based Phase-Frequency Detector

    Hello guys,
    i'm trying to understand the output of my phase detector only for a pulse that goes from zero to one.

    i'm trying to substitute the clocks initial values into the circuit and try to calculate the output, but since we have SR latches in this example that i'm showing, what should be the other values and what is the assumption?
    why this circuit can't go to meta-stability state?

    Note: all the gates are transistor level and not idea.

    these are the schematics and the value that I substituted and the simulation:


    Click image for larger version. 

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    Click image for larger version. 

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ID:	156018

    as you see, the up starts with 0.7 volts, and I don't know how to explain that.

    thanks in advance for any kind of help.

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  2. #2
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    Re: Output of Nand Sequential based Phase-Frequency Detector

    You didn't report the transistor technology.

    I presume you can see how the intermediate level is achieved if you look at all voltage. I guess it's a result that will be never observed in a real circuit due to component variations.



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