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Protecting the inputs of HV7802 current monitor from damage due to inrush current

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treez

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Page 4 of the HV7802 datasheet (RHS of page, 2nd paragraph down), states that adding a resistor into the LOAD pin gives protection for the HV7802.
It states that there is a bias current at the LOAD input which causes an offset due to this LOAD pin resistor…however, the next paragraph says that there is no offset due to bias current because it is a CMOS input and has zero bias current……which sentence do I believe?

I take it that ideally, the RA pin resistor, and the LOAD pin resistor, should be of the same value? (this obviously assumes there is a bias current)
HV7802
https://ww1.microchip.com/downloads/en/DeviceDoc/HV7802 A062813.pdf
 

Hi,

Datasheet says:
The protection resistor may cause an offset voltage due to
bias current at the LOAD input. A 100kΩ protection resistor
could cause an offset of 100µV, or 0.2% of full scale, under
worst case bias current. Note that bias current is nominally
zero
since LOAD is a high impedance CMOS input, resulting
in zero bias current induced offset voltage.
(corrected according post#3: uA --> uV)
100uV @ 100,000 Ohms is a current of 1nA.

Nominally the bias current is zero.....but you - as an experienced designer - should know that "zero" is impossible in the real world.
Maybe you woory about the word "bias current" --> then let´s name it "leakage current".

***
Any BJT will have true base current (bias current), it can`t work as an amplifier without base current. The current is calculable by I_C / B.
But a CMOS does no need a gate current to work. It is just unwanted leakage current.


Klaus
 
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I think that should be 100uV not uA Klaus ..... but we know what you mean :-D

Brian.
 
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Hi,

For sure you are right.
Not to cause any confusion with my formula, I corrected it.

Thanks

Klaus
 
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I take it that ideally, the RA pin resistor, and the LOAD pin resistor, should be of the same value?

Why? It's not suggested in the datasheet and doesn't seem to make sense. Ra is the gain setting resistor, and typically much smaller than the discussed Rp value.

Having nominally zero bias with nA maximum leakage is a typical CMOS input specification, really nothing special.
 
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