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    CMOS FINFET Layout Tutorials/Explanations

    What are the best resources (papers, books etc) to learn FINFET layout ?

    Can anyone share any ?

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    Re: CMOS FINFET Layout Tutorials/Explanations

    The best resources are documents and training materials from the foundries.
    Which is foundry proprietary and confidential.
    Meaning - you can see that only on the job, working for one of the companies using these technologies.

    Nothing that is available in the open literature comes close, in my opinion, to the real life.

    Max



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    Re: CMOS FINFET Layout Tutorials/Explanations

    Quote Originally Posted by Puppet123 View Post
    What are the best resources (papers, books etc) to learn FINFET layout ?

    Can anyone share any ?
    there is nothing special about a FinFET transistor. You have less flexibility than in older technologies. You will never draw a fin, for instance. It is always there, it is gridded and always present. You only have to align to it. You pretty much get 2 transistor templates from the foundry and you drop them into your layout. Things get a little messier when you get to the middle layers (M0), the connection rules are very wonky.
    Really, I am not Sam.



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    Re: CMOS FINFET Layout Tutorials/Explanations

    There are actually quite a lot of unusual and even counter-intuitive effects with FinFETs and with interconnects / parasitics in FinFET technologies.

    For example, gate resistance may go up as gate width gets smaller.

    Another example is the magnitude, number, and complexity of parasitics.

    And this list goes on...



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    Re: CMOS FINFET Layout Tutorials/Explanations

    Quote Originally Posted by timof View Post
    There are actually quite a lot of unusual and even counter-intuitive effects with FinFETs and with interconnects / parasitics in FinFET technologies.

    For example, gate resistance may go up as gate width gets smaller.

    Another example is the magnitude, number, and complexity of parasitics.

    And this list goes on...
    Agreed. The effects are wild, the layout is not. That was my point.
    Really, I am not Sam.



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    Re: CMOS FINFET Layout Tutorials/Explanations

    Yes, agreed, the layout still contains polygons.
    But, if you look at the FinFET layout (devices with interconnects), you can tell immediately it is not a planar CMOS technology.
    The style is completely different.
    To the contrary, if you look at planar technology layout, it's hard to tell if that is 90nm, or 65nm, or 40nm.

    Also, the amount of efforts required to make a clean and good (electrically) layout in FinFET nodes is much more than that for planar CMOS technology layouts.



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    Re: CMOS FINFET Layout Tutorials/Explanations

    Well, by all means let me be the first to "Google it" for you.

    https://www.google.com/search?q=finfet%20tutorial

    See? Easy and effective. You can do it. Yes you can.



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    Re: CMOS FINFET Layout Tutorials/Explanations

    If only doing real FinFET design layouts - with all their constraints, parasitics bottlenecks, complexity of multi-patterning, nonlinear effects, etc. etc. - would be that simple...

    "I know karate, jiujitsu, sambo, judo, kungfu, and many other dangerous words" :)



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    Re: CMOS FINFET Layout Tutorials/Explanations

    i just want to learn how to do it. also not all PDKs offer "any help" or tutorials - especially on how to do layout.

    i am going to answer my own question here: i will use Microwind to learn how to do FINFET layout. Then I can move on to the PDKs.

    https://www.microwind.net/products
    https://www.microwind.net/microwind_3_8

    If I could google it, no reason to come here right ?



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  10. #10
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    Re: CMOS FINFET Layout Tutorials/Explanations

    This video shows, approximately, how does layout for 7nm technology look like:

    https://www.youtube.com/watch?v=6xqx1-XOCv0



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