Haraldovs
Newbie level 3
Hello,
As a part of my master thesis i need to formally verify with completeness that the AHB
system I am using works as intended. I am using a vhdl ahb system generator found online, but
I wrote simple masters and slaves myself, so I need to make sure I haven't misunderstood the spec.
It looks from the spec and the master from the system generator that for a single transfer
the hbusreq is only kept high until the grant is given, and not during the address phase.
According to the diagrams granted master will not lose the address bus until its address phase
is over, and same for the databus.
My counterexamples show me that the address bus can get lost at any point, to a higher priority master.
Am i suppose to keep hbusreq high after all?
If not than I have poorly designed masters and slaves and it makes for a verification
nightmare on top of that.
Any input here is much appreciated.
As a part of my master thesis i need to formally verify with completeness that the AHB
system I am using works as intended. I am using a vhdl ahb system generator found online, but
I wrote simple masters and slaves myself, so I need to make sure I haven't misunderstood the spec.
It looks from the spec and the master from the system generator that for a single transfer
the hbusreq is only kept high until the grant is given, and not during the address phase.
According to the diagrams granted master will not lose the address bus until its address phase
is over, and same for the databus.
My counterexamples show me that the address bus can get lost at any point, to a higher priority master.
Am i suppose to keep hbusreq high after all?
If not than I have poorly designed masters and slaves and it makes for a verification
nightmare on top of that.
Any input here is much appreciated.
