Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Reverse polarity protection with FET is somewhat blighted by CDG capacitance

Status
Not open for further replies.
T

treez

Guest
Hi,
It is necessary to provide reverse polarity protection for a 24W Buckboost LED driver with Vin = 8 to 136VDC. (when vin <18v, then power can be reduced to 2W).
I find that the diode D3 is needed to mitigate the current that comes through the drain_gate capacitance of the reverse polarity fet at supply-ON time. –Especially when Vin is negatively greater than -100V.
The simulator may be over-exaggerating the D-G capacitance of the FET……do you know how I can inspect how much D-G capacitance is in this FET in the LTspice simulator? (and how the simulator changes this capacitance with VDG?)
LTspice sim and pdf schem attached.
 

Attachments

  • Reverse polarity protection.pdf
    12.1 KB · Views: 92
  • Reverse polarity protection.txt
    3.5 KB · Views: 36

Review the LTspice help for MOSFET VDMOS model. Together with the Vgd model parameters, you can calculate th assumed capacitance and compare with datasheet values.

I believe, you can easier compensate Cgd by a capacitor in parallel with gate source, e.g. some 10 nF.

A problematic point is exposing the drain terminal without overvoltage protection, e.g. a TVD diode. Vds,max is exceeded in your simulation circuit due to "line inductance" oscillations.
 
  • Like
Reactions: treez

    T

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top