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What things we need to take care a lenghty routing let's say 5000um

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saran826

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Hi what things we need to take care of a lengthy routing of 5000um?
what if its a voltage signal?
what if its a current path?

Please explain in detail what things we need to take care in these 2 cases?
 

In general, I would care about long line resistance, RC delay, capacitive coupling (accepting or introducing noise from/to other nets).

For current paths - IR drop (because of high resistance).

For voltage paths - capacitive coupling, introducing noise.

For extraction and post-layout analysis - do not forget to tell the extraction tool to fracture the line (set the maximum allowable fracturing length), otherwise all coupling capacitance will be assigned to the end points (if there are no fractures / vias / bents in this line), and your AC / transient response will be wrong, in post-layout simulations.
 

If its a very high frequency signal, you need to take care that it is not behaving as a transmission line.
 

Beware what's nearby. I had an ASIC respin once when
the autorouter decided to route a 60MHz and a 90MHz
clock side by side for 3000um and it made for about 100pS
of deterministic jitter (60MHz clock was beat forward,
then back, every other cycle by the 90MHz up / down
edges C-coupling on to the neighbor. Static timing analysis
didn't have anything for this. But SPICE on the extracted
netlist showed it (if you knew which two traces of the
40Kgate timing unit logic core, to even think about looking
at, prior to mask fab).

You might be better off putting "repeaters" every 1000um
or so, to keep driving impedance and "victim extent" low.
If you do then beware duty cycle error accumulation when
using noninverting buffers, if (say) the signal is sent outside
and might be tested against a duty +/- tolerance spec, or
some care-about product is sensitive to clock average DC /
duty cycle.
 

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