Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Difference between TRN and AXI4-Stream

Status
Not open for further replies.

buenos

Advanced Member level 3
Joined
Oct 24, 2005
Messages
960
Helped
40
Reputation
82
Reaction score
24
Trophy points
1,298
Location
Florida, USA
Activity points
9,116
What's the difference between TRN and AXI4-Stream interfaces?
I implemented a PCI-express transaction layer logic that worked on the Spartan-6 device. The PCIe endpoint IP had a TRN interface that simply passed the TLP packet to the user logic, my user logic that decoded the TLPs for generating local wishbone bus transactions.
Now I want to make the same thing on Kintex Ultrascale device, but its PCIE-EP IP has an AXI4-Streaming interface instead of TRN. It seems a lot more complicated. The specs show that the axi stream has a "descriptor" headers with all kinds of data like address and so on. But if a complete TLP is pased to user logic, while the PCIe standard TLP also has most of those fileds.
Question: The Ultrascale PCIe IP Axi bus descriptor is redundant with the TLP header, or the TLP passed to my user logic is incomplete? What should I do with descriptor header, can I just ignore it?
Anyone experience with this?
 

Ive never used TRN, but looking at the datasheet it is similar to AXI4 Streaming. First of all, everything is active high in AXI
dst_rdy = tready
src_rdy = tvalid
teof = tlast
trem = tkeep
td = tdata
tsrc_dsc and tbuf_av will probably be put into tuser, if they are used at all (reading the doc theres a lot of signals in tuser)
there is no SOF marker in AXI. You assume the first word after a tlast is SOF (so its common to either accept the first word as SOF or synchronise to a tlast. But Xilinx put SOF in tuser)

It looks like the Ultrascale core does some of the packet processing for you and passes the TLPs out of separate interfaces.
 

From what I have read, the new core still provides the full TLP, but adds an AXI header to it. The TRN provided only raw data.
When a pcie packet arrives, and I get a TLP on axi, possibly I can reject it. But for read requests, I have to generate a completion packet and assemble an additional AXI header to it, which is a lot of extra work.
The other thing is if both the TLP header and the axi header contain the same information, then this design from xilinx seems wasteful and silly. Or if the TLP is truncated and and an AXI header is provided instead of the TLP header, then I need to know about it. Unfortunately I could not find any info about this. The lack of info means the truncation does not happen, or the info is hidden in the documentation?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top