Mai89
Junior Member level 2
I need some help to implement this architecture please
:
assume that (function constant and modular) are implemented
Some notes from the paper i'm working on:
" This is a message scheduler, which uses sixteen shift registers (64-bits). Shift Registers are
loaded with the padded message blocks which require 16-clock cycles. For N rounds of operation, register 15 (R14) is replaced with the result of an equation (I) from message scheduler on the next clock cycle"
If this note is unclear plz ask me.
:assume that (function constant and modular) are implemented
Some notes from the paper i'm working on:
" This is a message scheduler, which uses sixteen shift registers (64-bits). Shift Registers are
loaded with the padded message blocks which require 16-clock cycles. For N rounds of operation, register 15 (R14) is replaced with the result of an equation (I) from message scheduler on the next clock cycle"
If this note is unclear plz ask me.
