UART TX signalling from another process

Hello all my post readers,

I am very new to FPGA, a weak ago started playing with a spartan 6. (Papilio pro). Now connected a 320x240 LCD to it and planning to do something with that as a hello world. I have a decent experience on electronics hardware, digital circuits and embedded firmware development. But first time with FPGA. Learning VHDL now.


I started with some documents and getting started guide from Papilio website.
Now able to understand the vhdl and it's syntax to an extent.

I did a small UART TX as my first program. It is working fine.

Now I want to keep that UART TX as a function equivalent. I want to keep that uart_tx: process(CLK) as a module and from another process I want to trigger the UART stat state machine.

I am able to trigger from external process by setting a 1 bit signal variable. I can read it from uart_tx process but I cannot clear it from there because yes two processes cannot asynchronously write to a single signal, I can imagine this.

So generally how people do this ?

Because I want to keep the UART TX isolated from other code and don't want to write anything inside that process. And if possible I want to keep it as a seperate file aswell so that I can invoke transmit trigger and set transmit byte from other vhdl file or other process in same file.

I can think of another option which is something like keeping two counter incrementing (at least 1 bit or higher) so that I just need to increment both counters on sending trigger(from main process) and sent complete response (from uart_tx process/uart seperate tx library file). But I am sure this may be a dirty way.

Can someone throw some light?

Also I have another question, all independent statements under a process will happen parallel and dependent things will follow sequential. Is this correct?

A bit difficult to visualise from an embedded programmer point of view.

Syncrhonizers are used to transfer a signal between clock domains.

Assuming that the UART and your trigger code are using different clock domains:

trigger code -> trigger signal -> synchronizer -> UART code

UART clear -> synchronizer -> trigger clear -> trigger code

Also I have another question, all independent statements under a process will happen parallel and dependent things will follow sequential. Is this correct?

A bit difficult to visualise from an embedded programmer point of view.

Click to expand...

VHDL is a hardware description language so much of the software paradigm does not translate directly

Statements in a CLOCKED process will have the RHS of the statements evaluated and the LHS will be updated when the process suspends.
Combonational processes will be entered any time a signal in the sensitivity list is updated. Statements in the process are in order of their appearance from what I remember from the LRM.

I avoid writing code that requires order of statement execution in a process to work correctly, that is the coding style that many SW coders seem to gravitate towards as it is more inline with the software paradigm they are familiar with.