Xilinx_Modelsim
Newbie level 4
Hi everyone,
I have a question about simulation (30MHz -> 1Hz clock divider).
I used a VHDL code and Modelsim Tool for clock divider.
Then, I want to get a simulation result about 50% duty cycle of 1Hz clock.
I got a result for my simulation about 0.499s rising clock and 0.98 falling clock.
*How can I get a accurate simulation result of 50% duty cycle 1Hz clock?
Thanks for your advices.
I have a question about simulation (30MHz -> 1Hz clock divider).
I used a VHDL code and Modelsim Tool for clock divider.
Then, I want to get a simulation result about 50% duty cycle of 1Hz clock.
I got a result for my simulation about 0.499s rising clock and 0.98 falling clock.
*How can I get a accurate simulation result of 50% duty cycle 1Hz clock?
Thanks for your advices.