Simulation about 30MHz -> 1Hz clock divider

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity Clock_Divider is
port ( clk,reset: in std_logic;
clk_out: out std_logic);
end Clock_Divider;
 
architecture bhv of Clock_Divider is
 
signal count: integer:=0;
signal tmp : std_logic := '0';
 
begin
 
process(clk)
begin
if(clk'event and clk='1') then
  count <=count+1;
  if (count = 15015015) then
    tmp <= NOT tmp;
    count <= 1;
  end if;
end if;
clk_out <= tmp;
end process;
 
end bhv;
-----------------------------------------------------------------------------
*** testbench ***
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY Tb_clock_divider IS
END Tb_clock_divider;
 
ARCHITECTURE behavior OF Tb_clock_divider IS
 
-- Component Declaration for the Unit Under Test (UUT)
 
COMPONENT Clock_Divider
PORT(
clk : IN std_logic;
reset : IN std_logic;
clock_out : OUT std_logic
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
 
--Outputs
signal clk_out: std_logic;
 
-- Clock period definitions
constant clk_period : real := 30000000;
constant clk_1 : time := 1/clk_period;
constant rising_time : time := clk_1/2;
constant falling_time : time := clk_1 - rising_time;
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
uut: Clock_Divider PORT MAP (
clk => clk,
reset => reset,
clk_out=> clk_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for falling_time;
clk <= '1';
wait for rising_time;
end process;

END;

-- Clock period definitions
constant clk_period : real := 30000000;
constant clk_1 : time := 1/clk_period;