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How to declare a variable number of parameters

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pbernardi

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Hello,

In Verilog, I would like to declare some initial parameters which influence the number of parameters to be defined later into the code. For example:

Code: 
parameter NUMBER_OF_A = 1;
parameter NUMBER_OF_B = 3;
parameter NUMBER_OF_C = 2;

(...)

parameter A1 = 8'd0;
parameter B1 = 8'd1;
parameter B2 = 8'd2;
parameter B3 = 8'd3;
parameter C1 = 8'd4;
parameter C2 = 8'd5;

So, if I change the NUMBER_OF_A, NUMBER_OF_B or NUMBER_OF_C, I would have different parameters defined on next lines. I tried to use some mix between parameter, vectors and generate without success. Any ideas?
 

In your example you have unique parameter names which must be assigned and referenced individually. What's the problem with having some unused parameters in your module? It's however possible to define parameter arrays with variable bounds, e.g.
Code Verilog - [expand]
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parameter A = 2,
parameter B = 5,
parameter real a[1:A] = '{1.52,2.34e5},
parameter integer b[1:B] = '{1,2,3,4,5},
 

Did you try compiler directives? You can get it done with
Code: 
`define
but it might look ugly.
 

FvM said:
In your example you have unique parameter names which must be assigned and referenced individually. What's the problem with having some unused parameters in your module? It's however possible to define parameter arrays with variable bounds, e.g.
Code Verilog - [expand]
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parameter A = 2,
parameter B = 5,
parameter real a[1:A] = '{1.52,2.34e5},
parameter integer b[1:B] = '{1,2,3,4,5},
Click to expand...

Thanks for the answer FvM.

What's the problem with having some unused parameters in your module?

I gave a simplified example to make my point, but in my real code, when I change NUMBER_OF_A, NUMBER_OF_B, and NUMBER_OF_C, it generates additional HW which uses the parameters generated (in this example, A1, B1, B2...etc.). If I generate unused parameters, it will reflect with additional real HW. In my case, this is bad because I am trying to find a good relation between parameters which generate an optimized HW, meaning additional parameter reflects in additional logic and decreased final frequency.

Please note hat my parameters will not be static, I really want to change it a lot to generate different scenarios. For example, if I changed NUMBER_OF_B to 4, I would like to have the parameters C1 shifted in values as well (B4 = 8'd4 and C1 starting in 8'd5 for example). So, in your example, I do not see how to change the number of vectors and its value dynamically (or is it possible)?

Lastly, to make thinks "simpler", I am using ISE 14.7, so this is Verilog and not System Verilog :-|

- - - Updated - - -

ThisIsNotSam said:
Did you try compiler directives? You can get it done with
Code: 
`define
but it might look ugly.
Click to expand...

I do not have problem in using `define but I still do not see how this might work. Could you please give an example?

Is it possible to used `define coupled with generate? I think it is not possible to generate multiple `define this way, but I am really not sure.
 

What do you mean with "dynamic"? Parameters are fixed at compile time, or in usual Verilog terms static.

Please note hat my parameters will not be static, I really want to change it a lot to generate different scenarios. For example, if I changed NUMBER_OF_B to 4, I would like to have the parameters C1 shifted in values as well
Click to expand...
I don't find this idea in the post #1 example. I think you did yet make clear what you want to achieve.

My solution is referring to the question in post #1 and the thread title. May be your real question is different.

If I generate unused parameters, it will reflect with additional real HW.
Click to expand...
No. Hardware is generated if actual module output depends on the parameter, otherewise the logic using the parameter is optimized away in synthesis. However, if a parameter is used in the logic, it can't be omitted in parameter list without generating a compilation error.
 

Hi FvM,

I don't find this idea in the post #1 example. I think you did yet make clear what you want to achieve.

Fair enough.

I want to have x different parameters, with y different values:

Code: 
parameter x1 = y1;
parameter x2 = y2;
(...)
parameter xn = yn;

and these parameters generates a list of k parameters (or define, or anything I can compare to a register) in compile time. Each one of these parameters generate a sequential value of that can be expressed in m bits (for example, if the last sequential values is 100, you need a m = 7 bits to accomplish this value).

Code: 
// all parameters below expressed in "m" bits;
parameter kx1[1] = 1; //The name kx1[1] is not important here; can be any name where I can identify with a generate for comparison in real code
parameter kx1[2] = 2;
parameter kx1[3] = 3;
(..) 
parameter kx1[y1] = y1;
parameter kx2[0] = y1 + 1;
parameter kx2[1] = y1 + 2; 
(...)
parameter kx2[y2] = y1 + y2;
parameter kx3[0] = y1 + y2 + 1;
parameter kx3[1] = y1 + y2 + 2;
(...)
parameter kx3[y3] = y1 + y2 + y3;
(...)
parameter kxn[yn] = y1 + y2 + y3 + (...) + yn;

I know the "code" above is not verilog, but I just cannot find a better way to express myself. So I will give another example, based on my initial post:

if I use:

Code: 
parameter NUMBER_OF_A = 1;
parameter NUMBER_OF_B = 1;
parameter NUMBER_OF_C = 1;

I would like to have the following values;

Code: 
//parameter names can be expressed as array, vector or whatever way I can identify later into the code; Not necessarily as A1, B1, C1, etc., could be A[1], B[1], C[1] for example.
parameter A1 = 2'd1; 
parameter B1 = 2'd2; 
parameter C1 = 2'd3;

if I modify the initial parameters to:

Code: 
parameter NUMBER_OF_A = 3;
parameter NUMBER_OF_B = 4;
parameter NUMBER_OF_C = 5;

I would like to have the following values expressed:

Code: 
//parameter names can be expressed as array, vector or whatever way I can identify later into the code; Not necessarily as A1, B1, C1, etc., could be A[1], B[1], C[1] for example.
parameter A1 = 4'd1; 
parameter A2 = 4'd2; 
parameter A3 = 4'd3; 
parameter B1 = 4'd4; 
parameter B2 = 4'd5; 
parameter B3 = 4'd6; 
parameter B4 = 4'd7; 
parameter C1 = 4'd8; 
parameter C2 = 4'd9; 
parameter C3 = 4'd10; 
parameter C4 = 4'd11; 
parameter C5 = 4'd12;

No. Hardware is generated if actual module output depends on the parameter, otherewise the logic using the parameter is optimized away in synthesis. However, if a parameter is used in the logic, it can't be omitted in parameter list without generating a compilation error.

In this case, as the number of bits defined in parameter changes, you would avoid code optimization. For example, you can generate a 8-bits mux instead a 3-bit mux because you have a parameter defined as 8-bits instead 3-bits. Or perhaps, you could have and 8-bits parameter compared to 3-bits registers and thus have uncovered cases.

Sorry if I omitted a lot of my intentions in my initial post, but I think I already have solutions for calculating the variation of "m" bits according the entered parameters; so I wanted really to focus on how to generate multiple parameters values based on some predefined initial parameters. The rest of work I think I can accomplish by myself.
 

I believe that everything you want to do can be achieved in Verilog, but I'm not sure if you are doing it in a straightforward way.
 

Hello,

I achieved what I needed, using generate/wires instead parameter. General idea of the code is the following (sorry for occasional mistakes, code not tested):

Code Verilog - [expand]
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parameter NUMBER_OF_A = 1;
parameter NUMBER_OF_B = 3;
parameter NUMBER_OF_C = 2;
parameter REG_SIZE = 3;
 
wire [REG_SIZE-1] A [1:NUMBER_OF_A];
wire [REG_SIZE-1] B [1:NUMBER_OF_B];
wire [REG_SIZE-1] C [1:NUMBER_OF_C];
 
genvar j;
 
generate
for(j=1;j!=NUMBER_OF_A;j=j+1)
begin:number_of_a
assign A[j] = j;
end
endgenerate
 
generate
for(j=1;j!=NUMBER_OF_B;j=j+1)
begin:number_of_b
assign B[j] = A[NUMBER_OF_A] + j;
end
endgenerate
 
generate
for(j=1;j!=NUMBER_OF_C;j=j+1)
begin:number_of_c
assign C[j] = B[NUMBER_OF_B] + j;
end
endgenerate


In this case, I can use wires as a "constant" instead a parameter.
 

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