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Decoupling Capacitance in IC Layo

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Puppet123

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Supply Decoupling Capacitance in IC Layouts

If doing an analog or RF layout, how much decoupling capacitance do you use in the layout for supply decoupling and, for RF layout, for supply feed line decoupling ?

How do you calculate these values ?
 

Hi,

With increasing frequency you may choose smaller (physically, as well as value) capacitors.
With increasing load ripple you may choose higher value capacitors.
They usually are not calculated ... they ate chosen by experience.

Target is to get stable supply voltage.
But for sure you can calculate them.
The you first need to know: frequency, expected ripple current at this frequency, expected voltage stability (ripple voltage)

* use Oh'm s law to calculate the (max) impedance for the supply source: Z = V_ripple/I_ripple
* use the capacitor_impedance_formula to calculate the (min) capacitance value. C = 1 / ( 2 x Pi x f x Z).

Urgent:
* correct type of capacitor: ceramics X7R --> NP0 (increasing frequency), no electrolytics because they are not suitable for HF
* very short wiring

Klaus

Added:
I just recognized that you talk about IC design. My answer is for PCB layout. :-(
 
If you have the other parasitics modeled clean all the way
from pins to transistor terminals, then you can play with
decoupling values and placement to get "as good as will
fit" supply quality where it counts.

But usually "will fit" dominates.

I like to replace foundries' dumb / useless density-fill
structure with cellular MOS/MOM cap stacks and also
under-pave bus-pairs with similar, larger ones. Mobetta,
just don't ignore that some caps have -too high- Q and
can cause more HF ringing on the internal supply lines,
than they remove (or, create a mysterious spur in the
frequency domain where they like to ring). Another job
for parasitics extraction / backannotation.
 

So you just add as much decoupling as you can depending on your layout at the IC level ?

Just any amount ?

- - - Updated - - -

Hi,

With increasing frequency you may choose smaller (physically, as well as value) capacitors.
With increasing load ripple you may choose higher value capacitors.
They usually are not calculated ... they ate chosen by experience.

Target is to get stable supply voltage.
But for sure you can calculate them.
The you first need to know: frequency, expected ripple current at this frequency, expected voltage stability (ripple voltage)

* use Oh'm s law to calculate the (max) impedance for the supply source: Z = V_ripple/I_ripple
* use the capacitor_impedance_formula to calculate the (min) capacitance value. C = 1 / ( 2 x Pi x f x Z).

Urgent:
* correct type of capacitor: ceramics X7R --> NP0 (increasing frequency), no electrolytics because they are not suitable for HF
* very short wiring

Klaus

Added:
I just recognized that you talk about IC design. My answer is for PCB layout. :-(

--

Thanks for the PCB advice, very helpful.
 

Make the Farad value sufficient so the DC voltage does not change too much from cycle to cycle. 5 or 10 percent ripple is easily noticed on an oscilloscope therefore it seems like a reasonable goal. You can shoot for 1 percent ripple although some might call that overkill.

The RC time constant gives a clue as to how much the voltage can be expected to change. Neighboring resistance needs to be known and accounted for.
 

I like to replace foundries' dumb / useless density-fill
structure with cellular MOS/MOM cap stacks and also
under-pave bus-pairs with similar, larger ones. Mobetta,
just don't ignore that some caps have -too high- Q and
can cause more HF ringing on the internal supply lines,
than they remove (or, create a mysterious spur in the
frequency domain where they like to ring). Another job
for parasitics extraction / backannotation.

To this point, I have a few questions.

When doing over 10 GHz amplifier designs, I usually tend to EM simulate the supply lines to determine the amount of RLC in the DC path and then use that to determine the amount of decoupling I would need.

If doing lower frequency designs (under 5GHz or Analog/Mixed signal designs) - I just use the RC extraction.

I am wondering if these methodologies/flows are the correct approach.

Finally, when doing high frequency broadband amplifiers (over 10GHz), I have use MIM caps for decoupling. However, I find that as you said, they cause ringing in the response typically at lower frequencies due to the high Q of the MIM caps. How can I eliminate this ringing ? Do I place some resistors in series with the MIM caps to dampen out the ringing at the cost of space and area ? Any other techniques ? Or just use MOS caps ? I would assume this ringing happens in all frequency (DC-over 10GHz) designs.

Thank you.
 

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