Mapuia
Junior Member level 3
A couple of weeks ago, I asked a question that involved Holtek's HT12E/HT12D encoder-decoder pair, although the issue was not mainly about them. Now I have a question that's more directly about these ICs.
My order of a batch of these ICs arrrived today and I immediately tried them out on a breadboard. I checked the minimum time they need to validate an input and was surprised to see that they need at least 80 milliseconds.
This is much longer than I expected. It's sixteen times the 5 msec needed by a different pair of ICs with a similar purpose - a Princeton PT2262/PT2272 pair. With each pair, I used oscillator resistor values typically shown in sample circuits.
Is the time required by the HT12E/HT12D reasonable? This data is important for my intended application. The datasheets are at
**broken link removed**
**broken link removed**
The encoder block diagram is on page 2 and the code is on page 5. For the decoder, these are on p2 and p4 respectively. I've tried to analyze the process from the datasheet but I have a limited understanding of these things. Please point out if and where I've made the wrong interpretation:
The encoder oscillator typically runs at about 3 kHz. This is internally divided by 3, resulting in a 1 kHz clock. One information word is about 24 clock cycles. One full packet of data is 4 words long or about 96 clock cycles or 288 oscillator cycles. Does this make any sense?
My order of a batch of these ICs arrrived today and I immediately tried them out on a breadboard. I checked the minimum time they need to validate an input and was surprised to see that they need at least 80 milliseconds.
This is much longer than I expected. It's sixteen times the 5 msec needed by a different pair of ICs with a similar purpose - a Princeton PT2262/PT2272 pair. With each pair, I used oscillator resistor values typically shown in sample circuits.
Is the time required by the HT12E/HT12D reasonable? This data is important for my intended application. The datasheets are at
**broken link removed**
**broken link removed**
The encoder block diagram is on page 2 and the code is on page 5. For the decoder, these are on p2 and p4 respectively. I've tried to analyze the process from the datasheet but I have a limited understanding of these things. Please point out if and where I've made the wrong interpretation:
The encoder oscillator typically runs at about 3 kHz. This is internally divided by 3, resulting in a 1 kHz clock. One information word is about 24 clock cycles. One full packet of data is 4 words long or about 96 clock cycles or 288 oscillator cycles. Does this make any sense?
