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10 millisecond counter with different frequencies

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tahirsengine

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I was designing a system, and the customer wanted to operate it on 10MHz.
There was a 10 Millisecond counter in that design, so I applied a 17 bit counter that gives a tick every 10 milliseconds based on this frequency. The code was like that:

Code:
  always @(negedge sys_rst_n or posedge sys_clk) begin
   if (~sys_rst_n) begin
      counter_tms      <=  17'b00000000000000000;
      counter_done     <=  1'b0;
   end else begin
      if(opmode != go_to_mode) begin
        counter_tms <= counter_tms + 1'b1;
        if (counter_tms >  17'b11000011010100000) begin
           counter_done <= 1'b1;
           counter_tms  <= 17'b00000000000000000;
        end else counter_done  <= 1'b0;
      end else begin
        counter_tms      <=  17'b00000000000000000;
      end
   end
end

Is there any method that no matter what sys_clk is, we are always count 10ms? I thought about parameterization, but how cant imagion that. Can some body help in this regards? For now, lets assume that frequency is 1 to 10MHz.
 

It depends if your goal is to have it change in real time, or parameterised before the build?
Either way, you need some mechanism to work out what the counter needs to count to based on the sys_clk frequency, which needs to be a parameter or control signal somehow.
 
It depends if your goal is to have it change in real time, or parameterised before the build?
Either way, you need some mechanism to work out what the counter needs to count to based on the sys_clk frequency, which needs to be a parameter or control signal somehow.

So may be I should include a port with a parameter, which will indicate which frequency it will operate on ?!
 

Do you understand the difference between port signals and parameters?

Unless the clock frequency is switched in operation, you want most likely to implement a clock frequency parameter. The counter bit width and compare value can be calculated at compile time in Verilog.
 
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