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26th September 2019, 08:52 #1
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SMPS power stage bode plot
Hi,
If asked for what is the "Power stage" bode plot of a SMPS, then I take that to mean the combination of the power stage and the modulator……ie not just the output filter and any transformers. Would you say that is what is meant by “power stage”?

26th September 2019, 17:18 #2
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Re: SMPS power stage bode plot
Hi, the modulator is not part of the power stage. You include the modulator gain when you are analyzing the loop gain  i.e. the uncompensated loop gain  just before you close the loop.

Akanimo.
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26th September 2019, 17:37 #3
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Re: SMPS power stage bode plot
I could imagine someone including the switches in the 'power stage'.
But regardless, the output filter should dominate its transfer function.

26th September 2019, 18:14 #4
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26th September 2019, 20:44 #5
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Re: SMPS power stage bode plot
there is a very slight effect from the capacitance of the power devices causing an extra slight delay due to rise time ( and fall time ) of the switched wave to the o/p filters  this can be ignored for straight power supplies  but gives a slight glitch for pwm inverters  esp where the o/p is higher than 50/60 Hz. ( similarly where miller effect produces a turn on and/or a turn off delay in the switching devices ).
The power stage gain is affected by the HVDC bus value also  if this goes up the o/p goes up
The modulator should be linear  i.e. for a 1V to 5V demand level in  the pwm goes from 0  99% ( curved sawtooth ramps are not linear  some on purpose )
just as a divider network of resistors from the o/p should be linear
Good luck.

26th September 2019, 23:21 #6
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Re: SMPS power stage bode plot
Depending on the topology, the modulator adds more or less dead time, e.g 1/2Fs for regular sampling, and in so far changes the transfer function.
In the block diagram of a complex system, the modulator might be subsumed to the power stage.
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28th September 2019, 11:10 #7
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Re: SMPS power stage bode plot
Thanks, as you know, the filter section of the power stage has no gain, except for at the resonant frequency of the LC in eg a buck converter in voltage mode. So when poeple draw a rough sketch of a power stage bode plot...they always show it starting at (zero Hertz) at around 20dB or so......but this gain depends on the modulator gain...would you agree?
For a current mode power supply, the modulator gain is any gain in the PWM control chip, plus the "R/Rs" gain , where R=LOAD and Rs = sense resistor ....why do people always seem to choose 20dB or so for this, in a rough sketch?

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28th September 2019, 13:37 #8
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Re: SMPS power stage bode plot
Hi,
The low frequency gain of a CCM buck is approx Vout/Duty. For DCM, it's a little bit more complicated.
Akanimo.

28th September 2019, 17:17 #9
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Re: SMPS power stage bode plot
Thanks, basically, would you agree that if someone draws the "power stage bode plot" of an smps and shows the gain plot starting at zero Hertz and with a gain at zero hertz of more than zero dB, then they must have included the "modulator" in with the "Power stage"...because the power stage filter has no gain at zero Hertz.
In fact the "power stage " never has positive gain unless its in voltage mode, and at the resonant frequency of the LC in the power stage?
The low frequency gain of a CCM buck is approx Vout/Duty. For DCM, it's a little bit more complicated.

28th September 2019, 19:05 #10
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Re: SMPS power stage bode plot
Of course I know that you are discussing the small signal transfer function and that expression that I wrote in post #8 is the low frequency gain of the controltooutput transfer function of an idealized CCM buck converter.
For the other question, there is no zero hertz. You can never get there. Before 1Hz, there is 0.1Hz. Before 0.1Hz, there is 0.01Hz. Then 0.001Hz, then 0.0001Hz. And so on. If you take a sample of PWM gains for known ICs, you would see that the PWM gain is a factor less than 1 (i.e. in ve dB). You are referring to the gain of the output filter. The gain of the output filter can never go above 1 (or 0dB) if it can even get there. But the transfer function of the output filter is just a part of the power stage transfer function.
The gain of the power stage can have a lowfrequency gain value greater than 1 and I just gave you that for the CCM buck.
Akanimo.
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18th October 2019, 10:06 #11
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Re: SMPS power stage bode plot
Hi treez,
Something just brought me to this thread and I just realized that you were asking for the lowfrequency gain expression for the controltooutput transfer function of a current mode buck converter power stage. For some reason I didn't sense that and the expression I gave you was for voltage mode.
The lowfrequency gain expression for a CCM buck in currentmode is Rload/Rsense.
I am really sorry for the confusion.
   Updated   
Peak current mode specifically.
Akanimo.
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18th October 2019, 22:31 #12
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Re: SMPS power stage bode plot
I believe that the power stage transfer function can be greater than 0dB for the case of voltage mode (not current mode) , and when at the resonant frequency of the LC of the power stage....(eg buck inductor/output capacitor resonance)
The control to output transfer function in current mode can never be greater than 0dB unless there is gain in the Modulator...
("control to output" = Power stage and modulator)

20th October 2019, 10:43 #13
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Re: SMPS power stage bode plot
No treez,
It can be seen from the controltooutput transfer function. Even the dc gain result you get after computing Rload/Rsense with modulator gain in the simple model would more likely be greater than 1.
Let's say you have a modulator gain of 1/4 = 0.25, then a ratio of Rload/Rsense = 4 would give a dc gain of 1 for the simple model and Rload/Rsense = 12 would give a dc gain of 3. . .and so on.
There is a more accurate model that is more involved but this simple model suffices to roughly demonstrate the dc gain being greater than 1.
   Updated   
This demonstration means to say that the dc gain =
(Rload/Rsense)*(Gmodulator=1/4).
Where Rsense is the physical sense resistor and Gmodulator is the modulator gain.
Akanimo.
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20th October 2019, 11:45 #14
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Re: SMPS power stage bode plot
Thanks, I previously thought that "Modulator gain" = [Rload/Rsense * gain factor]
And that the complete open loop comprises the "modulator", the "power stage", and the "error amplifier".
If asked to draw the control to output bode plot of say a current mode two transistor forward converter, at approximately what dB level would you start it off at zero Hertz? (or near zero Hertz, as i understand we do not get exactly to zero).
If asked to draw the general "Power Stage Bode plot" of a current mode two transistor forward converter, then you would start it off at 0dB?

20th October 2019, 17:13 #15
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Re: SMPS power stage bode plot
For forward converter, you have the same expression as for the buck converter except that Vin will now be n*Vin and Rsense will now be n*Rsense with n = Ns/Np.

Akanimo.
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21st October 2019, 02:00 #16
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Re: SMPS power stage bode plot
An open loop current mode controlled supply has a DC gain of infinity. A small current will infinitely charge the output capacitor. Load R brings that down, flattening the top of the bode plot.
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21st October 2019, 13:22 #17
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Re: SMPS power stage bode plot
"Power stage" isn't really standard terminology, but I would expect a bode plot to include the effect of the PWM modulator on the transfer function. Meaning that it should account for whether it's operating in DCM or CCM, and right half plane zeros, etc.
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23rd October 2019, 04:33 #18
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Re: SMPS power stage bode plot
Hi mtwieg,
We were discussing only the dc gain of the controltooutput transfer function for buck converters. We did not need to include poles and zeroes and, additionally, there is no RHPZ for buck.
Just like I mentioned in post #13, this is a simple model and it does not include the modulator voltage gain that you have to calculate. The simple model just gives the dc gain to be Rload/(Rsense*current_sense_gain) which when you equate to the expression I gave, namely (Rload/Rsense)*(Gmodulator), you get that Gmodulator that I gave is the reciprocal of the current sense gain given in your controller datasheet.
If you look up the datasheet of some controller ICs (like the wellknown UCx84x, UCC380x and other families  NOT that the ICs I mentioned are buck controllers but just to point to point to current sense gain values and to ), you will see a current sense gain value of 3 for the UCx84x family and 1.65 for the UCC380x family. These values would then translate to Gmodulator of 1/3 and 0.6 respectively in the expression that I gave.
There is a more accurate model but the simple model suffices for the discussion we are having on this thread.
Akanimo.
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23rd October 2019, 14:21 #19
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Re: SMPS power stage bode plot
I was addressing the original question, not any particular post...
When I do control analysis, my attention is always on the pole/zero locations. If I make a mistake estimating the magnitude of the transfer function, then correcting for it in the controller is trivial (it's only one parameter). Mistakes made in the phase response, on the other hand, may require totally redesigning the controller.
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