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[SOLVED] Post place & route netlist simulation is failing although STA is ok

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mifio

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Dear all,

I'm facing a problem with a post-pnr simulation that I hope you can help me figure out.

The design flow is based on the GPDK045 kit from Cadence. I use Genus & Innovus for synthesis & pnr, Modelsim for simulations, and I have compiled the standard cell library with modelsim for gate-level simulations.

Post-synthesis, my timing constraints are met and the simulation of the netlist+SDF works as expected. Post-pnr, my timing constraints are also met, however the simulation reports setup violations on many flops, which leads to erroneous results.

The design is a very simple processor core with only 1 clock. The target timing constraints is 1000 ps. Of course the test bench produces a matching clock of 1000 ps, but I even noticed that the problem remains with 1200 ps and 1500 ps.

The main reason why I need these gate level simulations is to generate the SAIF file for more accurate power evaluation. Also, my design being small the simulations (when working) are quite fast.

What I have tried/think-of so far:
  • I have used many sdf options in Innovus to generate the SDF, but basically I use -version 2.1 to match the standard cells, and -target_application verilog to optimize the sdf for simulations
  • I tried to do formal equivalence with the post-synthesis netlist but the version of the lec tool available has a bug.
  • Maybe a mismatch between the operating conditions used in the backend vs simulation ? Here I use the fast timing library (.lib) and qrc, and I compiled the fast version of the stdcell with modelsim.
  • Maybe a problem with the kit ? Anyone having a similar issue ?

I'm running out of idea, so I need your wisdom. Thank you very much for your time.
 

Dear all,

I'm facing a problem with a post-pnr simulation that I hope you can help me figure out.

The design flow is based on the GPDK045 kit from Cadence. I use Genus & Innovus for synthesis & pnr, Modelsim for simulations, and I have compiled the standard cell library with modelsim for gate-level simulations.

Post-synthesis, my timing constraints are met and the simulation of the netlist+SDF works as expected. Post-pnr, my timing constraints are also met, however the simulation reports setup violations on many flops, which leads to erroneous results.

The design is a very simple processor core with only 1 clock. The target timing constraints is 1000 ps. Of course the test bench produces a matching clock of 1000 ps, but I even noticed that the problem remains with 1200 ps and 1500 ps.

The main reason why I need these gate level simulations is to generate the SAIF file for more accurate power evaluation. Also, my design being small the simulations (when working) are quite fast.

What I have tried/think-of so far:
  • I have used many sdf options in Innovus to generate the SDF, but basically I use -version 2.1 to match the standard cells, and -target_application verilog to optimize the sdf for simulations
  • I tried to do formal equivalence with the post-synthesis netlist but the version of the lec tool available has a bug.
  • Maybe a mismatch between the operating conditions used in the backend vs simulation ? Here I use the fast timing library (.lib) and qrc, and I compiled the fast version of the stdcell with modelsim.
  • Maybe a problem with the kit ? Anyone having a similar issue ?

I'm running out of idea, so I need your wisdom. Thank you very much for your time.

This type of thread pops up here very regularly. You seem to be wiser than the typical poster, but maybe we should review the basics. The number one reason why gate level simulation fails is the testbench itself. It is very easy to get it wrong, there are problems with time units, with scope of variables, (wrong) assumptions about the input behavior, sync vs async issues, and so on. The second most common reason why the simulation fails is because of the SDF file itself not annotating correctly. You should be able to get some feedback from the simulator confirming that 100% of the instances have been annotated.

In your specific case, it appears that simulation only fails after P&R. This is an indication that clock is the issue, as now it no longer is ideal. Make sure your testbench is modelling it correctly. Also make sure the inputs are being generated correctly with respect to the clock edges. You should also investigate which flops are failing setup checks. Usually there is a pattern, it rarely is the entire design that fails at the same time. From the pattern you can try to reverse engineer what was the mistake.
 

Thank you for your answer,

You are right it never hurts to cover the basics. My test bench is in VHDL, I use ps as the default time units in the test bench, in simulation, in synthesis, and in pnr. The SDF is successfully annotated. As I mentioned, I even made sure to remove all the warnings that were due to inconsistencies between the SDF version used in the standard cells (v2.1) and the default version used in innovus (3.0).

The stimuli generated by the test bench are all synchronous to the clock, so I don't see any reason why they would cause the post-pnr simulation to fail and not the post-synthesis, granted that timing is met in both cases.

There is a pattern with the failing clocks: they are on the critical path (which makes sense).

The clock being the source of the issue is an interesting idea: Maybe the delayed timing evaluation is not done in the same way with Modelsim and Cadence STA engine. Though I tried the simulation with modelsim option +delayed_timing_checks without luck.

Any other ideas ?
 

I'm hardly an expert at doing ASIC STA and back annotated simulations anymore, but have you tried isolating the path in the simulation to see if the delays the simulator is showing match the same path in the STA? The last time I ever did this the timing was spot on between the two.
 

There is a pattern with the failing clocks: they are on the critical path (which makes sense).

Hmm. You need to debug gate by gate, see how much delay the simulation is showing vs how much STA is showing. It has to match very well.
 

Dear all,

I'm facing a problem with a post-pnr simulation that I hope you can help me figure out.

The design flow is based on the GPDK045 kit from Cadence. I use Genus & Innovus for synthesis & pnr, Modelsim for simulations, and I have compiled the standard cell library with modelsim for gate-level simulations.

Post-synthesis, my timing constraints are met and the simulation of the netlist+SDF works as expected. Post-pnr, my timing constraints are also met, however the simulation reports setup violations on many flops, which leads to erroneous results.

The design is a very simple processor core with only 1 clock. The target timing constraints is 1000 ps. Of course the test bench produces a matching clock of 1000 ps, but I even noticed that the problem remains with 1200 ps and 1500 ps.

The main reason why I need these gate level simulations is to generate the SAIF file for more accurate power evaluation. Also, my design being small the simulations (when working) are quite fast.

What I have tried/think-of so far:
  • I have used many sdf options in Innovus to generate the SDF, but basically I use -version 2.1 to match the standard cells, and -target_application verilog to optimize the sdf for simulations
  • I tried to do formal equivalence with the post-synthesis netlist but the version of the lec tool available has a bug.
  • Maybe a mismatch between the operating conditions used in the backend vs simulation ? Here I use the fast timing library (.lib) and qrc, and I compiled the fast version of the stdcell with modelsim.
  • Maybe a problem with the kit ? Anyone having a similar issue ?

I'm running out of idea, so I need your wisdom. Thank you very much for your time.

Some item you need to check :
1. Clock period ? Is it correct with your SDF .
2. Simulator option is correct with your SDF ? -mindelay with min conner and -maxdelay with max conner ? Using notiming check in your script ?
3. Your STA don't cover your pattern ? For example : this path is false_path in STA but in your pattern.
 

Thank you all for your precious help.

Today I had the time to dig in a bit more, and with your insight I found and solved the issues. As it was pointed out, the problem was actually with the test-bench and the clock.

I draw a sketch of the problem to better illustrate it.
Basically in the original test bench the same clock would feed both the core (post-pnr) and the memory (mem) which is a vhdl model, not a synthesized IP.
The problem is that on the rising edge of the clock, when a signal changes in the memory bus (here from 1 to 0) the clock that is supposed to capture its previous state in the core is delayed by the clock tree delay (represented by plain buffers). Since the memory has no delay, some flop would see a glitch, and some other would see a wrong value. The one seeing a glitch triggered the setup violation from the standard cell model.
To solve the problem I delayed the clock feeding the memory by an amount close to the IO delay constraint that I put on my sdc (represented by the dashed buffers). The new clock signal for the memory is derived from he main clock as follow: mem_clk <= transport clk after IO_DELAY;
Note that the IO_DELAY value is important: With a value too small I get the same setup error as I would without it, and with a value too big I get erroneous results when I write to the memory. Maybe having a read and write clock on the memory would be better.

During this debug I also solved other issues such as an (asynchronous, active low) reset false_path that was missing, which I also better modeled in the test bench.

postRoute_sim-issue.png
 

What I would do in the future is take the signals between the memory model and the UUT and add delays to the signals passing to/from the memory model, these would be values you derive from the layout and the memory datasheet. I'd do that before just delaying the memory clock until the simulation passes
 

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