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  1. #1
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    Xilinx synthesis directives within a VHDL 2008 package definition

    I am using Xilinx Vivado 2018.3.
    I tried to use the synthesis directives 'synthesis translate_off/on' within a VHDL 2008 package definition.

    The xsim compiler gave me errors for that. Are the directives not supported at that place?

    I have consulted UG901, Chapter2, and there it is only mentioned that "This attribute can only be set in the RTL." In my opinion the package definition part is also a valid RTL region.

    Or is this problem Xilinx specific?
    Any info on how other synth tools behave when these directives are used within a VHDL 2008 package definition?
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    Re: Xilinx synthesis directives within a VHDL 2008 package definition

    Dpaul, try the following

    constant sim_byte_endian : boolean := false
    -- pragma synthesis_off
    or true
    -- pragma synthesis_on
    ;
    constant syn_byte_endian : boolean := not sim_byte_endian;

    I am using this in vivado 2018.2

    --------------Edit

    I believe the reason for this behaviour might be one comment is a synopsis flavour whereas the other is supposedly in the language.

    I could say something about Ieee document 10766-2004, but to be honest it doesn't even give an example like I gave above.

    It talks about metacomments -- RTL_SYNTHESIS OFF / -- RTL_SYNTHESIS ON
    Last edited by wesleytaylor; 25th September 2019 at 10:00.



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  3. #3
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    Re: Xilinx synthesis directives within a VHDL 2008 package definition

    Thanks for your comment. I used pragma instead of synthesis, but still xsim throws errors.


    Code:
    .
    .
    constant DISK_LB_SIZE                               : MEMORY      := 8 KiB;
    constant DISK_LB_BLOCK_COUNT                        : natural     := 6;
    -- pragma translate_off
    constant DISK_LB_SIZE                               : MEMORY      := 512 Byte;
    constant DISK_LB_BLOCK_COUNT                        : natural     := 1;
    -- pragma translate_on
    constant BLOCK_SIZE_IN_MB                           : natural     := 32;
    .
    .
    Am I using it correctly?
    Can you please show an actual code snippet or use my code snippet example?
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    Re: Xilinx synthesis directives within a VHDL 2008 package definition

    Well in my design. IT works for synthesis. However I didn't use xsim for simulation because it couldn't handle vhdl2008.

    Examples of
    if rst then

    killed the xsim. It just cannot handle inferred (??) operator. Therefore I'm not surprised if it cannot handle pragma commands. Give RTL_SYNTHESIS OFF a go, if that fails then you're in a situation where Xilinx can handle it for synthesis but not simulation.



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    Re: Xilinx synthesis directives within a VHDL 2008 package definition

    I use them in a package without a problem, but I dont use Xsim.
    Maybe it's a bug. - raise on xilinx forum



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  6. #6
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    Re: Xilinx synthesis directives within a VHDL 2008 package definition

    @wesleytaylor, Thanks!. Probably it works only in synthesis. But in my requirement it shouls work in sim & synth.

    @Tricky, It is a little over 24hrs I have posted this issue in the Xilinx forums. They are yet to reply.
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