[SOLVED] hello can somebody help me what to do with generated quartus file .sdo .vho

hello to everyone
i start to work in quartus on timing analyzer
but i have problem i connected all input output to clok

and quartus say no error, but timing is red slack problem
and he generate some file .vho and .sdo file

what to do with those files

i open gate simulation and i compile(because i search it in internet)
but nothing change, what to(how to change timing) can somebody help please
thanks

michael 1978 said:

hello to everyone
i start to work in quartus on timing analyzer
but i have problem i connected all input output to clok

Click to expand...

what does this statement mean? what do you mean connected all input output to clock? how is this related to using timing constraints?
What are your timing constraints? Why didn't you provide them in the first post, so nobody has to ask you for them?

michael 1978 said:

and quartus say no error, but timing is red slack problem

Click to expand...

Again what timing constraints? Failing timing constraints isn't an error unless routing can't finish at all.

michael 1978 said:

and he generate some file .vho and .sdo file

what to do with those files

Click to expand...

you don't do anything with those files as I recall they are just some intermediate output files. You want to look at the report files. FYI quartus documentation has what file extensions used and tells you what they are for. I don't use Intel parts so I haven't read the docs for years, but I do remember seeing those files, but never needed to look at them.

michael 1978 said:

i open gate simulation and i compile(because i search it in internet)
but nothing change, what to(how to change timing) can somebody help please
thanks

Click to expand...

Gate level simulation is NOT how you change timing it only tells you how the design netlist behaves with the current place and route results. Random internet searches are not the way to learn. You should go on Intel's site and read their tutorials it is much better than some random google result.

ads-ee said:

what does this statement mean? what do you mean connected all input output to clock? how is this related to using timing constraints?
What are your timing constraints? Why didn't you provide them in the first post, so nobody has to ask you for them?

Again what timing constraints? Failing timing constraints isn't an error unless routing can't finish at all.

you don't do anything with those files as I recall they are just some intermediate output files. You want to look at the report files. FYI quartus documentation has what file extensions used and tells you what they are for. I don't use Intel parts so I haven't read the docs for years, but I do remember seeing those files, but never needed to look at them.


Gate level simulation is NOT how you change timing it only tells you how the design netlist behaves with the current place and route results. Random internet searches are not the way to learn. You should go on Intel's site and read their tutorials it is much better than some random google result.

Click to expand...

thank you
i just want to tell, that
i learn from free courses to design ALU from free courses, cousera Introduction to FPGA Design for Embedded Systems
by University of Colorado Boulder


so time input delay max 3 and min 2 ns and output time delay is max 2 ns and min 1 ns and clock is 8 ns,
i dont know how to do? what do you think to doi learn it from that course to design.

michael 1978 said:

so time input delay max 3 and min 2 ns and output time delay is max 2 ns and min 1 ns and clock is 8 ns,
i dont know how to do? what do you think to doi learn it from that course to design.

Click to expand...

This is a description of the requirements it isn't the contents of the SDC file you should be posting (if you want any useful help).

Did you even create an SDC file?

There is a free online course on the Intel website on how to meet timing using the TimeQuest Timing Analyzer. Go through the course with a bit of practice. Obviously the issue is on the setup time or hold time constraints that you provided in the tool.

ads-ee said:

what does this statement mean? what do you mean connected all input output to clock? how is this related to using timing constraints?
What are your timing constraints? Why didn't you provide them in the first post, so nobody has to ask you for them?

Again what timing constraints? Failing timing constraints isn't an error unless routing can't finish at all.

you don't do anything with those files as I recall they are just some intermediate output files. You want to look at the report files. FYI quartus documentation has what file extensions used and tells you what they are for. I don't use Intel parts so I haven't read the docs for years, but I do remember seeing those files, but never needed to look at them.


Gate level simulation is NOT how you change timing it only tells you how the design netlist behaves with the current place and route results. Random internet searches are not the way to learn. You should go on Intel's site and read their tutorials it is much better than some random google result.

Click to expand...

hello do you know any good tutorial free?

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ads-ee said:

This is a description of the requirements it isn't the contents of the SDC file you should be posting (if you want any useful help).

Did you even create an SDC file?

Click to expand...

hello thanks
i solved

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Akanimo said:

There is a free online course on the Intel website on how to meet timing using the TimeQuest Timing Analyzer. Go through the course with a bit of practice. Obviously the issue is on the setup time or hold time constraints that you provided in the tool.

Click to expand...

hello i solved, but i search but there are a little tutorial on youtube

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hello just one more question so i solved i make wrong clock speed,
so now i have problem to find the correct pins on pin planner of assigment editor
do you have any ide of any tutorial how to select the corrects pins

thnx to everyone

How do you mean "to select the correct pin"? At the minimum, you very much need the device datasheet.

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Also in the pin planner, mere placing the cursor on a pin would display info about that pin. You could reference the pin legend.

Akanimo said:

How do you mean "to select the correct pin"? At the minimum, you very much need the device datasheet.

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Also in the pin planner, mere placing the cursor on a pin would display info about that pin. You could reference the pin legend.

Click to expand...

yes that is true, but i dont understand all pin legend, for that i am searching tutorial to explain more in detail, because i am scare to make any mistake for example to put iniput to output in fpga and i can damage the fpga, like i learn from that cursus because i put all the pins from cpu in pin planner, so everything is correct i just get warning no errors

sorry for me late answer, thanks to everyone i solved
greetings