Dear all,
I have verilog block for which i have created symbol. I tried to test only that block performing AMS simulation and it works. Now i try to put it the actual design and perform AMS simulation. It gives the following error.
Please help me understand this.


Running netlist assembly..
ncvlog: *E,BADBSE (digital/netlist.vams,515|17): illegal base specification: (,) [2.5][2.5.1(IEEE)].
ncvlog: *E,EXPRPA (digital/netlist.vams,515|21): expecting a right parenthesis (')') [12.1(IEEE)].
ncvlog: *E,BADBSE (digital/netlist.vams,517|13): illegal base specification: (;) [2.5][2.5.1(IEEE)].
ncvlog: *E,EXPSMC (digital/netlist.vams,519|4): expecting a semicolon (';') [12.3.2(IEEE)].
irun: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (stat