+ Post New Thread
Results 1 to 1 of 1
  1. #1
    Newbie level 1
    Points: 20, Level: 1

    Join Date
    Sep 2019
    Posts
    1
    Helped
    0 / 0
    Points
    20
    Level
    1

    Error to run simv when using VCS to simulate both Verilog and Vhdl

    I can use vcs-mx-2016 to simulate verilog or vhdl.
    When I tyied to simulate vhdl and verilog in the same project, I was able to compile file with vhdlan and vlogan. However I got a error that event debug mode not supported, when I was excuting the generated file simv.
    "Error-[SC_RUNNING_PCODE] event debug mode not supported
    You are running '1' design unit(s) : 'DEFAULT.FULL_ADDER(SYNTH)' in event
    debug mode which is not supported in this release.
    Please contact Synopsys support for further assistance."
    Click image for larger version. 

Name:	6R_XB8@)S~ZKHZVE{2NPF0K.png 
Views:	2 
Size:	13.5 KB 
ID:	155594
    Last edited by wbr; 19th September 2019 at 02:22.

    •   AltAdvertisement

        
       

--[[ ]]--