Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Error to run simv when using VCS to simulate both Verilog and Vhdl

Status
Not open for further replies.
W

wbr

Newbie level 1
Joined
Sep 19, 2019
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
14
I can use vcs-mx-2016 to simulate verilog or vhdl.
When I tyied to simulate vhdl and verilog in the same project, I was able to compile file with vhdlan and vlogan. However I got a error that event debug mode not supported, when I was excuting the generated file simv.
"Error-[SC_RUNNING_PCODE] event debug mode not supported
You are running '1' design unit(s) : 'DEFAULT.FULL_ADDER(SYNTH)' in event
debug mode which is not supported in this release.
Please contact Synopsys support for further assistance."
6R_XB8@)S~ZKHZVE{2NPF0K.png
 
Last edited:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top