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18th September 2019, 22:44 #1
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parameterized insertion of bits to data
Hi, I am trying to implement something and I want to fully parameterize it. I will explain the problem.
My data comes into a MUX and I choose which data to accept. then I have some extra bits that need to get appended to this data. These 'number of bits to be appended " will be a parameter.
so we have
Code:input [3:0] data1; input [3:0] data2; input [3:0] data3; input [1:0] control; input [2:0] append_data; parameter bits_to_append = 1;
So as you can see, the bits that get appended needs to be controlled. So my MUX will select its first data, append the 1st bit. Then the MUX needs to select the next data depending on the control, and append the next part of the additional data. Is there any way to implement a for loop over this MUX?

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18th September 2019, 23:30 #2
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Re: parameterized insertion of bits to data
One again with the vague descriptions.
Draw a detailed picture and post it along with an example not in Verilog that shows what you are attempting, i.e. an example of the operations.
And no I can't see, as the code you provided doesn't show anything about how you are "appending" the append_data. Unless there is some pattern to the appending then any kind of loop will fail to implement what you want.

18th September 2019, 23:46 #3
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Re: parameterized insertion of bits to data
I thought it was evident that I am talking about data getting appended at the end. But seeing how it wasn't, I will try my best to make it clear. Just to clarify, i am talking about concatenation operation. Once data is selected, the extra bits get concatenated at the end. Then the next operation of data selection needs to begin based on the next control that is received. With this new data, the next chunk of additional data should get appended.
So basically,
1. Based on select bits, choose first data; append chunk of bits from additional data at the end of our input data.
2. Based on second select input, choose second set of data; append the next chunk of bits from additional data at the end of this data.

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19th September 2019, 00:08 #4
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Re: parameterized insertion of bits to data
I don't understand either.
Please show an example with sample data input and output values. How is control used? What order to the bits in append_data get selected? What happens when bits_to_append is larger or smaller than bits in append_data?Dave Rich
Senior Verification Consultant
Mentor Graphics Corporation

19th September 2019, 00:10 #5
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Re: parameterized insertion of bits to data
bits_to_append wont be larger than the data to append. It is parameterized and I choose the value. bits_to_append will decide the chunk of data from append_data that will be concatenated with our input data each time.

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19th September 2019, 08:07 #6
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Re: parameterized insertion of bits to data
I think the output is 4*InputWidth + 4*bits_to_append in width. If this is the case, the locations of the added bits is known and easy to calculate.

19th September 2019, 17:23 #7
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Re: parameterized insertion of bits to data
What I have drawn is just an example. It will keep repeating with a lot of data. But the width of append_data is fixed. After the bits are finished, we start appending 0's.
How do I make it happen every time new data gets selected? I need the block to know which bit of the append_data was appended last in order to append the next bit with the new input data.
I tried implementing a for loop over my case statements but it doesnt work.Last edited by rrucha; 19th September 2019 at 17:45.

19th September 2019, 20:15 #8
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Re: parameterized insertion of bits to data
Because as I've told you before, a software paradigm doesn't fit with how you write code for HDLs.
FOR loops are unrolled spatially not sequentially, i.e. for loop are used to replicate logic (spatial) not set the order of events (sequuence). You use an FSM to keep track of the ordering of events.
As I've mentioned previously, draw the circuit that does what you want (don't write HDL until you know how to design the circuit) then translate that circuit to an HDL. If you do it this way you will understand what the HDL is going to produce when synthesized.

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19th September 2019, 21:20 #9
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20th September 2019, 23:13 #10
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Re: parameterized insertion of bits to data
I tried an FSM implementation but the two operations seem to never work together. Getting new data in every clock and appending the next bit of the append_data are not getting synchronized.
   Updated   
Hi,
No what i drew was only an example.
Basically in 1st clock, 1st stream of input data will be clocked in and appended with the 0th bit of the append_data.
In 2nd clock, 2nd stream of input data will be clocked in and appended with the 1st bit of append_data
And so on.
So append_data is fixed like a parameter and input_data keeps changing every clock (new data keeps coming in)
They are all given as individual outputs in each clock cycle.
   Updated   
control is an input that tells me which data out of the three inputs to use. 1 bit of append_data will get selected every cycle and is in the order of append_data[0] then append_data[1] ..... append_data[7] (assuming append_data is 8 bits wide).
Its always smaller than append_data. Lets just assume for convenience sake that bits_to_append is always set to 1. So a single bit gets appended every cycle.

21st September 2019, 08:45 #11
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Re: parameterized insertion of bits to data
I tried an FSM implementation but the two operations seem to never work together. Getting new data in every clock and appending the next bit of the append_data are not getting synchronized.
Have you got a circuit diagram yet?
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