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Physical Verification with TSMC65nm CRN65LP PDK

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Puppet123

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Now I was told for my version of Calibre 2017, I have to do the following for this PDK:


In LVS rule file add:


LAYOUT CELL LIST pcells “rf component here*” “rf component here*”
LAYOUT PRESERVE CELL LIST pcells


In PEX rule file add:


Use XCELL file, add -I option at end.

rf component here* rf component here -I
rf component here* rf component here -I


Where rf component here is the pcell that should not be double counted (if the rf model of an nmos or pmos)


I assume I am adding all the RF components, transistors, passives (caps) etc in the LVS rule file that I have in the foundry provided PEX XCELL file.

Is this correct ?

What is an HCELL file ? What is an XCELL file ? What is the purpose of the source added file ?

Thank you.
 
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